Performance of the DAQ system of the PANDA Micro-Vertex Detector

Abstract

The Micro-Vertex Detector (MVD) is the innermost subdetector of the PANDA (anti-Proton ANnihilations at DArmstadt) detector at FAIR. Its microstrip sensors are read out by custom front-end electronics called ToASt (Torino ASIC for Strip readout) [1]. The ToASt chips are locally managed by an MDC (Module Data Concentrator) [2]. The MDC processes incoming event data and forwards them to the off-detector readout cards based on the AMC (Advanced Mezzanine Card) standard. Both the MDC and the AMC readout card are currently under development at KIT [3]. The complete readout chain, including the double-sided microstrip sensor read by the ToASt chips and the FPGA implementation of the MDC, was successfully tested during a 2023 beam test at COSY (Forschungszentrum Jülich). This proof-of-concept validation of the MDC logic paves the way for the forthcoming ASIC version of the MDC, which is planned for submission in February 2025. Extensive performance characterization of the current readout chain has been achieved with the MDC-FPGA optically connected to an AMD-Xilinx ZCU102 evaluation card [4], which emulates the AMC off-detector card, through a Versatile Link+ Demo Board (VLDB+) [5]. This contribution presents the MDC-ASIC design, its integration with both the front-end and back-end electronics and the performance results of the complete readout chain.