Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy

Gordon‐Ross, Ann; Lau, Jeremy; Calder, Brad

doi:10.1145/1366110.1366200

Cited by 33 publications

(40 citation statements)

References 13 publications

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“…Later, Ross et al [7] described an extension to enable dynamic cache reconfiguration. However, they do not describe the control signals required to combine way-concatenation with way-shutdown.…”

Section: Way-only Reconfigurationmentioning

confidence: 99%

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The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

Sundararajan

Jones

Topham

2012

Int J Parallel Prog

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The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-application-phase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and are therefore prime candidates for adaptation.Fixed-configuration caches must be designed to deliver low average memory access times across a wide range of potential applications. However, this can lead to excessive energy consumption for applications that do not require the full capacity or associativity of the cache at all times. Furthermore, in systems where the clock period is constrained by the access times of level-1 caches, the clock frequency for all applications is effectively limited by the cache requirements of the most demanding phase within the most demanding application. This results in both performance and energy efficiency that represents the lowest common denominator across the applications.In this work we present a Set and way Management cache Architecture for Run-Time reconfiguration (SMART cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energydelay of the Smart cache is on average 70% and 12% better than the baseline configuration for a two-core and four-core system respectively, with just 2% away from oracle result and also with an overall performance degradation of less than 2% compared with a baseline statically-configured cache.

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Section: Way-only Reconfigurationmentioning

confidence: 99%

“…Dynamic cache reconfiguration is not a new topic, having been previously studied by a variety of researchers [1][2][3][7][8][9]24,31,32]. These schemes monitor the miss ratio at run-time, reconfiguring the cache whenever it reaches a certain threshold value.…”

Section: Introductionmentioning

confidence: 99%

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

Sundararajan

Jones

Topham

2012

Int J Parallel Prog

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show abstract

“…However, they did not address the changes required to the control signals when adding in way-shutdown. Later, Ross et al [5] described an extension to enable dynamic cache reconfiguration. However, they do not describe the control signals required to combine way-concatenation with way-shutdown.…”

Section: B Way-only Reconfigurationmentioning

confidence: 99%

“…Dynamic cache reconfiguration is not a new topic, having been previously studied by a variety of researchers [2], [3], [4], [5], [6], [7], [8], [9], [10]. These schemes monitor the miss ratio at run-time, reconfiguring the cache whenever it reaches a certain threshold value.…”

Section: Introductionmentioning

confidence: 99%

Smart cache: A self adaptive cache architecture for energy efficiency

Sundararajan

Jones

Topham

2011

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-applicationphase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and are therefore prime candidates for adaptation.Fixed-configuration caches must be designed to deliver low average memory access times across a wide range of potential applications. However, this can lead to excessive energy consumption for applications that do not require the full capacity or associativity of the cache at all times. Furthermore, in systems where the clock period is constrained by the access times of level-1 caches, the clock frequency for all applications is effectively limited by the cache requirements of the most demanding phase within the most demanding application. This results in both performance and energy efficiency that represents the lowest common denominator across the applications.In this paper we present a Set and way Management cache Architecture for Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 14% better than state-of-the-art cache reconfiguration architectures. We then leverage the flexibility provided by our cache to dynamically reconfigure the hierarchy as a program runs. We develop a decision tree based machine learning model to control the adaptation and automatically reconfigure the cache to the best configuration. Results show an average reduction in energy-delay product of 17% in the data cache (just 1% away from an oracle result) and 34% in the level-2 cache (just 5% away from an oracle), with an overall performance degradation of less than 2% compared with a baseline statically-configured cache.

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“…To increase optimization potential by specializing system resources to varying application characteristics, we leverage phase-based tuning [8] as a complementary approach to DFS. A phase is a length of execution during which an application's characteristics remain relatively stable.…”

Section: Introductionmentioning

confidence: 99%

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Adegbija

Gordon‐Ross

2017

Computers

Self Cite

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Embedded systems have stringent design constraints, which has necessitated much prior research focus on optimizing energy consumption and/or performance. Since embedded systems typically have fewer cooling options, rising temperature, and thus temperature optimization, is an emergent concern. Most embedded systems only dissipate heat by passive convection, due to the absence of dedicated thermal management hardware mechanisms. The embedded system's temperature not only affects the system's reliability, but can also affect the performance, power, and cost. Thus, embedded systems require efficient thermal management techniques. However, thermal management can conflict with other optimization objectives, such as execution time and energy consumption. In this paper, we focus on managing the temperature using a synergy of cache optimization and dynamic frequency scaling, while also optimizing the execution time and energy consumption. This paper provides new insights on the impact of cache parameters on efficient temperature-aware cache tuning heuristics. In addition, we present temperature-aware phase-based tuning, TaPT, which determines Pareto optimal clock frequency and cache configurations for fine-grained execution time, energy, and temperature tradeoffs. TaPT enables autonomous system optimization and also allows designers to specify temperature constraints and optimization priorities. Experiments show that TaPT can effectively reduce execution time, energy, and temperature, while imposing minimal hardware overhead.

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Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy

Cited by 33 publications

References 13 publications

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

Smart cache: A self adaptive cache architecture for energy efficiency

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

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