Phase-Change Memory in Neural Network Layers with Measurements-based Device Models

Abstract

The search for energy efficient circuital implementations of neural networks has led to the exploration of phasechange memory (PCM) devices as their synaptic element, with the advantage of compact size and compatibility with CMOS fabrication technologies. In this work, we describe a methodology that, starting from measurements performed on a set of real PCM devices, enables the training of a neural network. The core of the procedure is the creation of a computational model, sufficiently general to include the effect of unwanted nonidealities, such as the voltage dependence of the conductances and the presence of surrounding circuitry. Results show that, depending on the task at hand, a different level of accuracy is required in the PCM model applied at train-time to match the performance of a traditional, reference network. Moreover, the trained networks are robust to the perturbation of the weight values, up to 10% standard deviation, with performance losses within 3.5% for the accuracy in the classification task being considered and an increase of the regression RMS error by 0.014 in a second task. The considered perturbation is compatible with the performance of state-of-theart PCM programming techniques.

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

“…When a voltage x k is introduced across a PCM device with conductance configured to w j,k and outputs an electrical current i j,k is equal to w j,k × x k . The conductance is regarded as constant and unaffected by the applied voltage in this presumption this methodology is a well-liked use of PCM technology and in the paper [101] to suggest a universal training strategy for neural networks with PCM-based layers. Within the neural network layers, PCM arrays have been used in numerous applications [102].…”