Photonic NoC for DMA Communications in Chip Multiprocessors

Shacham, A.; Lee, Benjamin G.; Biberman, Aleksandr; Bergman, Keren; Carloni, Luca P.

doi:10.1109/hoti.2007.4296805

Cited by 42 publications

(76 citation statements)

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“…The physical implementation and performance of this photonic NoC is discussed in [15] and its power consumption is analyzed in [13]. Its main organization is illustrated in Fig.…”

Section: A Hybrid Approach To Noc Designmentioning

confidence: 99%

Photonic networks-on-chip: Opportunities and challenges

Petracca

Bergman

Carloni

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-As the number of processing cores that are integrated into a chip multiprocessors (CMP) continues to grow, the network-on-chip paradigm has emerged as a promising solution to address the problem of providing a robust interconnect network among them. In future high-performance CMPs, however, the high bandwidth requirements for both intrachip and off-chip communication are severely challenging the electronic communications infrastructure to meet these demands without consuming a large fraction of the overall on-chip powerdissipation budget. The introduction of photonic technology for on-chip communication holds the promise of delivering scalable bandwidth-per-watt performance that cannot be achieved using only electronic communication. After reviewing the key recent technologies advances that are making possible the integration of photonic devices with CMOS processes, we describe a hybrid micro-architecture for NoCs that combines a broadband photonic circuit-switched network with an electronic packet-switched control network and we discuss the pros and cons of using two different network topologies to implement it.

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“…The physical implementation and performance of this photonic NoC is discussed in [15] and its power consumption is analyzed in [13]. Its main organization is illustrated in Fig.…”

Section: A Hybrid Approach To Noc Designmentioning

confidence: 99%

Photonic networks-on-chip: Opportunities and challenges

Petracca

Bergman

Carloni

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…While the actual switching of the optical components can nowadays be done in a mere 30 ps [4], the latency in setting up this optical channel will be at least one round-trip time of a control message on the lower speed electrical NoC. This means that such a photonic NoC [5] will only be beneficial when communicating large chunks of data (KiB's) between processor cores. As the majority of traffic in shared-memory processors consists of short memory and coherence messages (with a size of about one cache line, usually only 64 bytes), the promised benefits of low-power photonic NoCs will fail to materialize under an unchanged shared-memory model of current CMPs.…”

Section: Introductionmentioning

confidence: 99%

Architectural study of reconfigurable photonic Networks-on-Chip for multi-core processors

Artundo

Heirman

Loperena

et al. 2009

2009 IEEE LEOS Annual Meeting Conference Proceedings

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Abstract-Photonic Networks-on-Chip (NoCs) have become a promising route to interconnect processor cores on chip multiprocessors (CMP) in a power efficient way. Although several photonic NoC proposals exist, their use is limited to the communication of large data messages due to a relatively long set-up time for the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically to the evolving traffic situation. This way, long photonic channel set-up times can be tolerated which makes our approach more compatible in the context of shared-memory CMPs.

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“…In previous work, we have studied electronically controlled circuit-switched photonic NoCs, arranged in a variety of two-dimensional (2-D) topologies [1], [7]. The most prevalent photonic network element in these topologies is the nonblocking four-port bidirectional router, which dynamically routes broadband messages to their target destinations.…”

Section: Introductionmentioning

confidence: 99%

“…Photonic networks-on-chip (NoCs) introduce a logical solution, since 1) photonic links provide very large bandwidths, methodically scalable with the wavelength parallelism of the optical domain, and 2) photonic messages can be exchanged in a highly energy-efficient manner [1]. Moreover, the equivalent [3], switches [4], [5], receivers [6]) have been demonstrated, and designers currently strive toward obtaining performance improvements and increasing the level of device integration.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the routing elements in these topologies must ideally provide four bidirectional input/output (I/O) ports, with multiwavelength routing capabilities and strictly nonblocking functionality. Such a router has been designed, and its network-level performance has been evaluated through simulations [1], [7]. Furthermore, the router was fabricated [8], and initial data characterizations were performed [9], [10].…”

Section: Introductionmentioning

confidence: 99%

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Broadband Operation of Nanophotonic Router for Silicon Photonic Networks-on-Chip

Biberman

Lee

Sherwood-Droz

et al. 2010

IEEE Photon. Technol. Lett.

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Abstract-A nonblocking four-port bidirectional multiwavelength message router for use in photonic network-on-chip (NoC) architectures implementing two-dimensional mesh or torus topologies is fully characterized with bit-error-rate measurements and eye diagrams using three wavelength-parallel 10-Gb/s channels. The experiments demonstrate the feasibility of using this advanced switching subsystem within dynamically routed multiwavelength photonic NoCs.

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Photonic NoC for DMA Communications in Chip Multiprocessors

Cited by 42 publications

References 0 publications

Photonic networks-on-chip: Opportunities and challenges

Photonic networks-on-chip: Opportunities and challenges

Architectural study of reconfigurable photonic Networks-on-Chip for multi-core processors

Broadband Operation of Nanophotonic Router for Silicon Photonic Networks-on-Chip

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