Placement Optimization of Flexible TFT Digital Circuits

The 2021 flexible and printed electronics roadmap

“…In addition to the FPE/FHE PDK, customized place-and-route (P&R) algorithms for physical design flow is also required in order to accommodate the bending use cases for TFT circuits. The study in [141] relied on a statistical timing analyzer (STA) to identify bending hotspots, and used the derived information together with TFT bending models [142] to generate a hotspot mapping for guiding circuit layout, followed by the cell placer's simulated annealing process for finding the optimized cell placement to minimize timing degradation under bending. The study in [143] further suggested inclusion of both mechanical strain and temperature drift's impacts on TFT circuit's performance in layout optimization.…”