PMM: a pipelined maximal-sized matching scheduling approach for input-buffered switches

Oki, Eiji; Rojas‐Cessa, Roberto; Chao, H. Jonathan

doi:10.1109/glocom.2001.965075

Cited by 15 publications

(9 citation statements)

References 15 publications

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“…At the end of a frame, the switch is configured according to the reservations made during the frame. In [36], RRGS is extended to address the fairness issue in handling inadmissible traffic patterns and to support a variable number of schedulers.…”

Section: A Relationship With the Work Inmentioning

confidence: 99%

Feedback-Based Scheduling for Load-Balanced Two-Stage Switches

Yeung

2010

IEEE/ACM Trans. Networking

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Abstract-A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unlike existing approaches, we show that the efforts made in load balancing and keeping packets in order can complement each other. Specifically, at each middle-stage port between the two switch fabrics of a load-balanced switch, only a single-packet buffer for each virtual output queueing (VOQ) is required. Although packets belonging to the same flow pass through different middle-stage VOQs, the delays they experience at different middle-stage ports will be identical. This is made possible by properly selecting and coordinating the two sequences of switch configurations to form a joint sequence with both staggered symmetry property and in-order packet delivery property. Based on the staggered symmetry property, an efficient feedback mechanism is designed to allow the right middle-stage port occupancy vector to be delivered to the right input port at the right time. As a result, the performance of load balancing as well as the switch throughput is significantly improved. We further extend this feedback mechanism to support the multicabinet implementation of a load-balanced switch, where the propagation delay between switch linecards and switch fabrics is nonnegligible. As compared to the existing load-balanced switch architectures and scheduling algorithms, our solutions impose a modest requirement on switch hardware, but consistently yield better delay-throughput performance. Last but not least, some extensions and refinements are made to address the scalability, implementation, and fairness issues of our solutions.Index Terms-Load-balanced switch, feedback-based switch, two-stage switch.

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Section: A Relationship With the Work Inmentioning

confidence: 99%

Feedback-Based Scheduling for Load-Balanced Two-Stage Switches

Yeung

2010

IEEE/ACM Trans. Networking

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“…Schemes based in round-robin matching, such as iSLIP [7], iDRRM [10], [11], and SRR [8] are examples of such schemes and these can deliver 100% throughput under uniform traffic with a single iteration. iSLIP showed that the desynchronization effect, where arbiters reach the point where each of them prefers to match with different input/outputs, is beneficial for switching under this traffic pattern.…”

Section: Introductionmentioning

confidence: 99%

Concatenating Packets in Variable-Length Input-Queued Packet Switches with Cell-Based and Packet-Based Scheduling

Al-Saber

Oberoi

Pedasanaganti

et al. 2008

2008 IEEE Sarnoff Symposium

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Abstract-Internet data is transmitted in variable-size packets to provide flexibility for different applications. There has been a growing interest in developing the design of Internet routers based variable-lenght packets to improve performance and reduce the amount of re-assembly memory. However, most of variable-length designs follow a time-slotted approach, which make them similar to routers that switch fixed-length packets. The use of slotted timing makes padding necessary when packet sizes are not proportional to the time-slot length. In this paper, we investigate the impact of concatenating packets to reduce the amount of padding in variable-length packet switches. This approach increases the utilization of interconnection bandwidth and overall throughput performance. Performance evaluation in an input-queued packet switch using packet concatenation is presented.Index Terms-Packet scheduling, input-queued switch, variable length packet, cell switching, packet-based scheduling, packet concatenation.

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“…Maximal-size matching are another way to resolve contention in IQ switches [3]. Schemes based in round-robin matching, such as iSLIP [4], DRRM [5], [6], and SRR [7] have been proposed to deliver 100% throughput under uniform traffic. iSLIP showed that the desynchronization effect, where arbiters reach the point where each of them prefers to match with different input/outputs, is beneficial for switching under uniform traffic.…”

Section: Introductionmentioning

confidence: 99%

Matching schemes with captured-frame eligibility for input-queued packet switches

Rojas‐Cessa

Lin

2005

IEEE International Conference on Communications, 2005. ICC 2005. 2005

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Abstract-Virtual output queues (VOQs) are widely used by input-queued (IQ) switches to eliminate the head-of-line (HOL) blocking phenomena, which limits switching performance. An effective matching scheme must provide high throughput under several admissible traffic patterns and keep implementation complexity low. A variety of matching schemes for IQ switches that deliver high throughput under uniform traffic have been proposed. However, there is a need of matching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions. In this paper, we introduce the captured frame-size concept for matching schemes in IQ switches. We use the captured-frame eligibility concept in a round-robin based scheme, uFORM, and in a random-base scheme, uFPIM, to improve switching performance under nonuniform traffic patterns. The uFPIM scheme is based in the parallel iterative matching (PIM) scheme and shows the throughput improvement achieved with the captured frame concept. The uFORM scheme provides high performance under nonuniform traffic while keeping the high performance that round-robin schemes are known to have under uniform traffic.Index Terms-input-queued switch, round-robin matching, virtual output queue, captured frame, frame eligibility, service frame, unbalanced traffic

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PMM: a pipelined maximal-sized matching scheduling approach for input-buffered switches

Cited by 15 publications

References 15 publications

Feedback-Based Scheduling for Load-Balanced Two-Stage Switches

Feedback-Based Scheduling for Load-Balanced Two-Stage Switches

Concatenating Packets in Variable-Length Input-Queued Packet Switches with Cell-Based and Packet-Based Scheduling

Matching schemes with captured-frame eligibility for input-queued packet switches

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