PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC

Sarkar, Sudipta; Yuan, Zhijun; Elies, Brian; Chiu, Yun

doi:10.1109/tcsi.2014.2373032

Cited by 22 publications

(7 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also, open‐loop gain A of op‐amp is required to large enough, so that

1 / A β \overset{yields}{\to} 0

and hence,

()(, 1 - 1 / A β) \overset{yields}{\to} 1

. All these factors deviate the stage gain from its ideal value of 2 and calibration is performed to calibrate pipelined ADC for one or more of these errors [7–9, 13–16, 19].…”

Section: Non‐idealities Analysis Of Pipelined Adcmentioning

confidence: 99%

“…According to whether ADC's operation is interrupted or not, digital calibration is divided into foreground calibration and background calibration, respectively. Background calibration technique detects and calibrates the pipelined ADC by using a reference ADC [7][8][9][10][11][12] or by applying some uncorrelated random sequence [13,14], while the ADC is continuously working. However, this technique lacks in precision estimations and takes thousands of cycles to calibrate.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Fast digital foreground gain error calibration for pipelined ADC

Kaur¹,

Prabhakar

Singh

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Here, a fast digital foreground calibration technique to calibrate the gain error in the pipelined analogue-to-digital converter (ADC) is proposed. The technique suggested uses maximum reference value of the ADC along with least mean squares adaptive algorithm to compensate the gain error. It avoids the use of slow but accurate reference ADC, thus saving area, power, and design efforts. The proposed calibration algorithm is implemented in Xilinx Artix-7 FPGA kit to show the effectiveness of the algorithm. After calibration, differential non-linearity improves by 30% and integral non-linearity reduces from values +60/−60 LSB to +0.77/-0.77 LSB. Also, signal to noise and distortion ratio and spurious-free dynamic range improve significantly from 35.9193 and 36.7348 to 75.3619 and 82.2884 dB, respectively, after calibration.

show abstract

“…Also, open‐loop gain A of op‐amp is required to large enough, so that

1 / A β \overset{yields}{\to} 0

and hence,

()(, 1 - 1 / A β) \overset{yields}{\to} 1

. All these factors deviate the stage gain from its ideal value of 2 and calibration is performed to calibrate pipelined ADC for one or more of these errors [7–9, 13–16, 19].…”

Section: Non‐idealities Analysis Of Pipelined Adcmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fast digital foreground gain error calibration for pipelined ADC

Kaur¹,

Prabhakar

Singh

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…This allows having different decision paths in a much simpler scheme, without limiting the conversion speed. A similar process was followed for pipelined-ADC calibration in [14], a difference being that in that approach a PN sequence is used instead of a constant delta. Fig.…”

Section: Proposed Split Adc: Split-deltamentioning

confidence: 99%

Split-Delta Background Calibration for SAR ADCs

Ramos

Verhelst

2017

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

This paper introduces a unified performance benchmarking framework which allows to map existing SAR mismatch calibration methods and compare their performance under identical circumstances. Using this framework, an analysis of advantages and disadvantages of popular state-of-the-art methods is presented. Combining the strengths of some of these methods leads to the proposal of a new calibration scheme, coined the split-delta method. This calibration approach is a modification of the split-ADC, yet avoids the more complex architectural modifications required by other split-ADC schemes, while preserving good convergence speed and performance. Finally, the effects that dynamic effects on top of capacitor mismatch and offset have on the converter's SNR are analyzed.

show abstract

“…Digital calibration algorithms are classified into foreground (Chang et al , 2004; Grace et al , 2004) and background (Moon and Song, 1997; Sarkar et al , 2015) techniques. The normal operation of the pipelined ADCs is interrupted in foreground calibrations while background techniques continuously detects and removes the errors.…”

Section: Introductionmentioning

confidence: 99%

“…The normal operation of the pipelined ADCs is interrupted in foreground calibrations while background techniques continuously detects and removes the errors. The most popular digital background calibration methods are categorized into histogram-based (Brooks and Lee, 2008; Gholami and Yavari, 2017), statistical-based (Mafi et al , 2018; Mafi et al , 2016), correlation-based (Panigada and Galton, 2006; Panigada and Galton, 2009) and deterministic (McNeill et al , 2009; Sarkar et al , 2015; Sehgal et al , 2015; Montazerolghaem et al , 2015; Zia et al , 2019). The priority of deterministic techniques over others is the faster calibration time.…”

Section: Introductionmentioning

confidence: 99%

New digital background calibration method for pipelined ADCs

Zia

Farshidi

Kosarian

2020

COMPEL

View full text Add to dashboard Cite

Purpose Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs. Design/methodology/approach The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix. Findings Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles. Practical implications The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results. Originality/value The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

show abstract

PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC

Cited by 22 publications

References 13 publications

Fast digital foreground gain error calibration for pipelined ADC

Fast digital foreground gain error calibration for pipelined ADC

Split-Delta Background Calibration for SAR ADCs

New digital background calibration method for pipelined ADCs

Contact Info

Product

Resources

About