Poly-CMP Slurry for Flash Memories

Abstract

IC market demand for flash memories showed a significant growth trend in recent years. In manufacturing of flash memories, one of the most important processes is forming floating gate or control gate, which is greatly influenced by gate-poly CMP performance. To prepare a floating gate or control gate, a poly-silicon (poly) layer will be deposited on the active area (AA) , which is between the STI trench structures, typically HDP oxide. Then through CMP technique, the overburdened poly will be removed, with no poly residue on the top of HDP surface and leaving a certain thickness of AA poly whose top surface is planar with HDP top surface. However, in the case that a poly layer and a silicon dioxide layer are being polished, the removal rate of poly-silicon will tend to be much higher than that of silicon dioxide, resulting in recess between the STI trench structures and a non-planarized surface. To overcome this issue, we report here a novel poly CMP slurry that has the self-stopping capability and good planarization efficiency, with which the excellent surface planarity, poly dishing and poly residue clearance were obtained on 300 mm patterned wafers.