Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

Pude, M.; Mukund, P.R.; Burleson, J.

doi:10.1002/cta.1929

Cited by 4 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The two two-stage op-amp circuits presented in [5,6] have designed 1.8 V using 0.18µm technology suffering with low gain and PMs, hence in this paper proposed an op-amp circuit as in Fig. 1.…”

Section: Design Of Op-amp Circuitmentioning

confidence: 99%

A 75 μW Two-Stage Op-Amp using 0.18μW CMOS Technology for High-Speed Operations

2019

View full text Add to dashboard Cite

Low voltage operated Analog and digital circuits have big demand due to its better performance. But, it leads to number of challenges. Operational amplifier is the basic element in most of the circuits, because of its wide advantages. Gain, bandwidth, linearity, noise and output swings are the design parameters. Operational amplifier design is unique for different applications. This paper presents the design of a 1.8V two-stage Operational amplifier using 0.18 µm CMOS technology for low power and high-speed operations. This design draws 5 µA current with 1.8 V and produced the gain of 87 dB, phase margin (PM) of 67 • and the unity gain bandwidth (GBW) of 4.87 MHz through AC analysis. The proposed design has a Slew rate of 4.126 V/µs, which determines the speed of the Operational amplifier. The input common mode range (ICMR) is improved to 0.07-1.65 V and the power dissipation is 75 µW.

show abstract

Section: Design Of Op-amp Circuitmentioning

confidence: 99%

A 75 μW Two-Stage Op-Amp using 0.18μW CMOS Technology for High-Speed Operations

2019

View full text Add to dashboard Cite

show abstract

“…One common technique to increase effective transconductance is to use positive feedback. 19 The structure shown in Figure 4 used this technique to improve the performance of the folded cascode amplifier. 20 The use of this technique leads to an increase in effective transconductance of the circuit, which results in improved voltage gain as well as unity gain bandwidth F I G U R E 4 Enhanced folded-cascode amplifier using local positive feedback technique (GBW).…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, increasing the gain of the circuit is associated with increasing the power consumption. One common technique to increase effective transconductance is to use positive feedback 19 . The structure shown in Figure 4 used this technique to improve the performance of the folded cascode amplifier 20 .…”

Section: Introductionmentioning

confidence: 99%

A low power CMOS programmable gain amplifier employing positive feedback technique

Firouz

Aghdam

Jafarnejad

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

This paper presents a low power CMOS programmable gain amplifier (PGA) utilizing a novel gm‐boosting technique to increase the maximum achievable DC gain. The structure increases the effective transconductance of the circuit without any additional elements. The gain enhancement is accomplished without increasing the power consumption. The variable gain function is achieved by varying the effective transconductance of the circuit and its output resistance. The proposed PGA achieves a wide gain range of 47.5 dB from 2.1 to 49.6 dB with a constant bandwidth. According to the post‐layout simulation results of the proposed circuit in 0.18‐μm TSMC CMOS process the bandwidth and the input referred noise voltage at the maximum gain are 11.3 MHz and 10.76 nV/sqrt (Hz), respectively. The second and third harmonic distortions of the proposed PGA at the minimum gain are less than −72.4 and −40.7 dB, respectively. The core circuit of proposed PGA draws only 164 μA from a 1.2‐V supply voltage occupying an area of 29 μm * 26 μm.

show abstract

“…However, in this technique chip area has been increased drastically. In other methods [19, 20], DC‐gain enhancement is obtained with the cost of UGBW decreasing. In [21], a folded cascode op‐amp has been proposed which improves DC gain using positive feedback technique.…”

Section: Introductionmentioning

confidence: 99%

Positive feedback technique and split‐length transistors for DC‐gain enhancement of two‐stage op‐amps

Anisheh

Shamsi

Mirhassani

2017

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

This study presents the design and simulation of a fully differential two-stage op-amp in a 0.18 μm complementary metal-oxide-semiconductor process with a 1.8 V supply voltage. In this op-amp, positive feedback technique and split-length transistors (SLTs) are employed to increase the DC-gain of the op-amp by about 22 dB without affecting the unity-gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two-stage op-amp. A comprehensive analysis is provided for differential-mode gain, common-mode gain, power supply rejection ratio, input-referred noise, input offset, frequency response and the effect of using SLTs on DC-gain sensitivity. The proposed op-amp is utilised in a flip-around sample-and-hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post-layout and Monte Carlo simulation results show that the proposed op-amp has better performance than the state-ofthe-art designs.

show abstract

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

Cited by 4 publications

References 12 publications

A 75 μW Two-Stage Op-Amp using 0.18μW CMOS Technology for High-Speed Operations

A 75 μW Two-Stage Op-Amp using 0.18μW CMOS Technology for High-Speed Operations

A low power CMOS programmable gain amplifier employing positive feedback technique

Positive feedback technique and split‐length transistors for DC‐gain enhancement of two‐stage op‐amps

Contact Info

Product

Resources

About