Post-layout optimization of power and timing for ECL LSIs

Abstract

An optimization algorithm for power and timing of Bipolar ECL LSIs is proposed. The power dissipation is minimized by a nonlinear programming solver under accurate timing constraints extracted f r om layout. The power and delay time of an ECL gate are c onsidered functions of its switching current which is regulated b y programming its resistors. Experimental results show signicant power reductions for circuits including a real chip without degrading the performance.