Power and Area-Efficient Architectural Design Methodology for Nanomagnetic Computation

In this study, we propose a nanomagnetic logic (NML) based 2 bit multiplier architecture design for the first time to the best of author’s knowledge. This complex combinational logic (nanomagnetic multiplier) design proposed is built by exploiting shape, positional hybrid anisotropy and the ferromagnetically coupled fixed input majority gate. Subsequently, we extend this proposed multiplier architecture along with the NML adder architecture in introducing NML based convolution architecture design which is efficient in terms of number of nanomagnets, majority gates and clock-cycles. The proposed NML design yields ∼21%–72%, ∼26%–42%, ∼36%–63%, and ∼20%–68%, reduction in the required number of nanomagnets, majority gate, clock cycles and energy compared to the state-of-the-art designs.

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Area efficient in-plane nanomagnetic multiplier and convolution architecture design

Sivasubramani

Debroy

Acharyya

2021

Nano Ex.

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Power and Area-Efficient Architectural Design Methodology for Nanomagnetic Computation

Cited by 1 publication

References 47 publications

Area efficient in-plane nanomagnetic multiplier and convolution architecture design

Area efficient in-plane nanomagnetic multiplier and convolution architecture design

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