Power and Area Efficient VLSI Architectures for Communication Signal Processing

Marković, Dejan; Nikolić, Borivoje; Brodersen, R.W.

doi:10.1109/icc.2006.255303

Cited by 11 publications

(5 citation statements)

References 9 publications

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“…Each twodimensional cost function is crucial for determining the best architecture that meets constrained design specifications. Figure 1 illustrates the trends in tradeoff curves between pairs of performance metrics for a hardware design space [17,18]. A closer look at the power-delay curve reveals an interesting and important design trend in digital circuits.…”

Section: Figures Of Meritmentioning

confidence: 98%

Automated Design Space Exploration for DSP Applications

Hourani

Jenkal

Davis

et al. 2008

J Sign Process Syst Sign Image Video Technol

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We present a performance analysis framework that efficiently generates and analyzes hardware designs for computationally intensive signal processing applications. Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation. Cost functions provided by our framework allow the user to reduce the design space to a set of efficient hardware implementations that meet performance constraints. We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold. This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs. Our work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. We illustrate the efficiency and accuracy of our framework by generating finite impulse response filter structures used in several signal processing applications such as adaptive equalizers and quadrature mirror filters. The results show that hardware filter structures generated by our framework can achieve, on average, a 3 fold increase in power efficiency when compared to manually constructed designs.

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Section: Figures Of Meritmentioning

confidence: 98%

Automated Design Space Exploration for DSP Applications

Hourani

Jenkal

Davis

et al. 2008

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

show abstract

“…Разработка экономически-эффективных алгоритмов цифровой обработки сигналов (в том числе для телекоммуникационных систем) явля ется одним из ключевых направлений развития электронной техники [1].…”

Section: постановка задачиunclassified

Design of programmable interpolation filter for ULSI digital modulator-converter

Alekseev

Glukhov

Rogulina

2012

2012 IEEE 11th International Conference on Actual Problems of Electronics Instrument Engineering (APEIE)

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“…The square root and division are implemented using Newton-Rhapson iterative formulas, which have quadratic convergence [9]. In implementation terms, this means that each iteration resolves two bits of accuracy [10]. Under slowly varying input, which is the case with MIMO channel data, the result can be taken as the initial condition for the next iteration to obtain the answer in a single iteration.…”

Section: Adaptive Blind-tracking Svd Algorithmmentioning

confidence: 99%

Power and Area Minimization for Multidimensional Signal Processing

Marković

Nikolić

Brodersen

2007

IEEE J. Solid-State Circuits

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Abstract-Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4 4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm 2 in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers.

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Power and Area Efficient VLSI Architectures for Communication Signal Processing

Cited by 11 publications

References 9 publications

Automated Design Space Exploration for DSP Applications

Automated Design Space Exploration for DSP Applications

Design of programmable interpolation filter for ULSI digital modulator-converter

Power and Area Minimization for Multidimensional Signal Processing

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