Power-aware branch prediction: characterization and design

Parikh, Dharmesh; Skadron, Kevin; Zhang, Y.; Stan, Mircea R.

doi:10.1109/tc.2004.1261827

Cited by 40 publications

(29 citation statements)

References 24 publications

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“…The branch has a bias to one behaviour. These kinds of branches can, in many cases, be seen to waste energy in the predictor since their predicted behaviour will be almost constantly the same [5] [8].…”

Section: Biased Branchesmentioning

confidence: 99%

“…Most embedded architectures are Reduced Instruction Set Computers [8]. Part of the benefit of this is the simplicity of the instruction format.…”

Section: Hint Bitsmentioning

confidence: 99%

“…The disadvantages of this method are that it requires that the processor's clock frequency is low enough to permit an I-Cache access and branch predictor access in series in one cycle and that there are enough redundant bits in all instructions. Hardware Complexity: Annotate only branch instructions with hint bits and use a hardware mechanism similar to a Prediction Probe Detector [8] to interpret hint bits. This has minimal effect on the instruction set.…”

Section: Hardware Requirements/modificationsmentioning

confidence: 99%

“…Mispredicting a branch direction wastes both time and power, by executing instructions in the pipeline which will not be committed. Research [8] [3] has shown that, even with their increased power cost, modern larger predictors actually save global power by the effects of their increased accuracy. This means that any attempt to reduce the power consumption of a dynamic predictor must not come at the cost of decreased accuracy; a holistic attitude to processor power consumption must be employed [7] [9].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation

Hicks

Egan

Christianson

et al. 2006

Advances in Computer Systems Architecture

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Abstract. Dynamic branch predictor logic alone accounts for approximately 10% of total processor power dissipation. Recent research indicates that the power cost of a large dynamic branch predictor is offset by the power savings created by its increased accuracy. We describe a method of reducing dynamic predictor power dissipation without degrading prediction accuracy by using a combination of local delay region scheduling and run time profiling of branches. Feedback into the static code is achieved with hint bits and avoids the need for dynamic prediction for some individual branches. This method requires only minimal hardware modifications and coexists with a dynamic predictor.

show abstract

Section: Biased Branchesmentioning

confidence: 99%

“…Most embedded architectures are Reduced Instruction Set Computers [8]. Part of the benefit of this is the simplicity of the instruction format.…”

Section: Hint Bitsmentioning

confidence: 99%

Section: Hardware Requirements/modificationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation

Hicks

Egan

Christianson

et al. 2006

Advances in Computer Systems Architecture

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“…Bimodal은 최근의 분기 결과를 BHT (Branch History [7] . 기존의 분기 예측기는 대부분 범용 프로세서를 기준으로 설계되므로 전력 소모가 많고 분기의 예측률을 높이기 위해 노력하 였다 [8][9][10][11] . [12] .…”

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An Improved Dynamic Branch Predictor by Selective Access of a Specific Element in 4-Way Cache

Hwang

2013

The Journal of Korean Institute of Communications and Informati

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In-sung Hwang , Sun-young Hwang°요 ABSTRACTThis paper proposes an improved branch predictor that reduces the number execution cycles of applications by selectively accessing a specific element in 4-way associative cache. When a branch instruction is fetched, the proposed branch predictor acquires a branch target address from the selected element in the cache by referring to MRU buffer. Branch prediction rate and application execution speed are considerably improved by increasing the number of BTAC entries in restricted power condition, when compared with that of previous branch predictor which accesses all elements. The effectiveness of the proposed dynamic branch predictor is verified by executing benchmark applications on the core simulator. Experimental results show that number of execution cycles decreases by an average of 10.1%, while power consumption increases an average of 7.4%, when compared to that of a core without a dynamic branch predictor. Execution cycles are reduced by 4.1% in comparison with a core which employs previous dynamic branch predictor.

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A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

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Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

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Power-aware branch prediction: characterization and design

Cited by 40 publications

References 24 publications

Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation

Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation

An Improved Dynamic Branch Predictor by Selective Access of a Specific Element in 4-Way Cache

A survey of techniques for dynamic branch prediction

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