Power Delivery for High-Performance Microprocessors—Challenges, Solutions, and Future Trends

Radhakrishnan, Kaladhar; Swaminathan, Madhavan; Bhattacharyya, Budhaditya

doi:10.1109/tcpmt.2021.3065690

Cited by 69 publications

(14 citation statements)

References 31 publications

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“…To control the CLM FIVRs voltage, we route an additional control signal, Ret, from the APMU to the two FIVRs that power the CLM [82]. To enable a FIVR to directly transition to a pre-programmed retention voltage, we add to each FIVR control module (FCM [12,67]) an 8-bit register that holds the retention voltage identification (RVID) value [63,74]. Finally, we add a PwrOk status signal that the FIVR uses to notify the APMU that the voltage is stable.…”

Section: Cha Llc and Mesh Retention (Clmr)mentioning

confidence: 99%

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers

Antoniou¹,

Volos²,

Bartolini³

et al. 2022

Preprint

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Modern user-facing applications deployed in datacenters use a distributed system architecture that exacerbates the latency requirements of their constituent microservices (30-250µs). Existing CPU power-saving techniques degrade the performance of these applications due to the long transition latency (order of 100µs) to wake up from a deep CPU idle state (C-state). For this reason, server vendors recommend only enabling shallow core C-states (e.g., CC1) for idle CPU cores, thus preventing the system from entering deep package Cstates (e.g., PC6) when all CPU cores are idle. This choice, however, impairs server energy proportionality since powerhungry resources (e.g., IOs, uncore, DRAM) remain active even when there is no active core to use them. As we show, it is common for all cores to be idle due to the low average utilization (e.g., 5 − 20%) of datacenter servers running user-facing applications.We propose to reap this opportunity with AgilePkgC (APC), a new package C-state architecture that improves the energy proportionality of server processors running latencycritical applications. APC implements PC1A (package C1 agile), a new deep package C-state that a system can enter once all cores are in a shallow C-state (i.e., CC1) and has a nanosecond-scale transition latency. PC1A is based on four key techniques. First, a hardware-based agile power management unit (APMU) rapidly detects when all cores enter a shallow core C-state (CC1) and trigger the system-level power savings control flow. Second, an IO Standby Mode (IOSM) that places IO interfaces (e.g., PCIe, DMI, UPI, DRAM) in shallow (nanosecond-scale transition latency) low-power modes. Third, a CLM Retention (CLMR) rapidly reduces the CLM (Cache-and-home-agent, Last-level-cache, and Mesh network-on-chip) domain's voltage to its retention level, drastically reducing its power consumption. Fourth, APC keeps all system PLLs active in PC1A to allow nanosecond-scale exit latency by avoiding PLLs' re-locking overhead.Combining these techniques enables significant power savings while requiring less than 200ns transition latency, >250× faster than existing deep package C-states (e.g., PC6), making PC1A practical for datacenter servers. Our evaluation using Intel Skylake-based server shows that APC reduces the energy consumption of Memcached by up to 41% (25% on average) with <0.1% performance degradation. APC provides similar benefits for other representative workloads.

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Section: Cha Llc and Mesh Retention (Clmr)mentioning

confidence: 99%

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers

Antoniou¹,

Volos²,

Bartolini³

et al. 2022

Preprint

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“…These efficiencies can be increased by either decreasing the effective resistance between the VR and die or/and integrating highvoltage conversion ratio regulators near the die on the same package. 18 For such integrated voltage regulators (IVR), the inductor serves as an energy storage element by delivering current to the output. The key performance metrics which are used to judge the performance of inductors are its energy density, quality factor, and saturation characteristics.…”

Section: Materials For Increasing Power Delivery Efficiencymentioning

confidence: 99%

“…However, the size, equivalent series resistance (ESR) and series inductance (ESL), and cost of the decoupling capacitor play a crucial role in determining the quality of power delivery, especially with the number of power rails being more than 50 in modern computing applications. 18 The trend for power delivery in HI is shown in Figure 3, where the objective is to maximize the power density while reducing interconnect length and module thickness. This requires the integration of two critical components namely, inductor and capacitor.…”

Section: Materials For Increasing Power Delivery Efficiencymentioning

confidence: 99%

“…Based on a trade-off between saturation current, inductance density, and DC resistance, the required properties of the magnetic material can be derived using the Lorentz and Landau-Lifshitz-Gilbert equation. 18,27 As an example, for a 48 V/1 V conversion @ 10 MHz with 90% efficiency, the magnetic material should have a permeability of ~ 90, loss tangent less than 0.033 at 10 MHz and stability up to 50 MHz. 28 However, most commercially available high-permeability materials have a loss tangent that is unacceptably high at frequencies of 10 MHz or higher, which becomes a bottleneck.…”

Section: Magnetic Materialsmentioning

confidence: 99%

“…As we move towards high-voltage IVRs with higher input voltage, we will need high-frequency decoupling for the input rail that can handle higher voltage. One possible alternative to high-voltage silicon capacitors is the development of highvoltage, high-frequency package capacitors such as thin-film capacitors 18,37 and embedded array capacitors. 38…”

Section: Dielectric (High D K ) Materialsmentioning

confidence: 99%

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Materials for heterogeneous integration

et al. 2021

Self Cite

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Emerging artificial intelligence (AI) applications require dense connectivity between integrated circuit (IC) chips to enable high-speed computations. Heterogeneous integration (HI) using advanced packaging is being viewed as a critical enabling technology for supporting AI applications. Such highly integrated systems require a multitude of materials to support electrical, mechanical, thermal, and chemical properties. In addition, these materials need to be compatible with packaging processes to ensure compatibility with low-cost manufacturing solutions. The inter-play between the various engineering domains makes the selection of materials, their processability, and compatibility extremely complex. In this article, we investigate the future in terms of the requirements posed by materials for HI and survey the past and present work in this area.

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Wafer‐Scale Integration

Safari¹,

Vaisband²

2022

Wiley Encyclopedia of Electrical and Electronics Engineering

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The key challenges of on‐chip integration, including limited scalability, high cost, difficulty to maintain profitable yield, and increased thermal management complexity, suggest that additional avenues for scaling should be explored. Wafer‐scale integration is the extension of the system‐on‐chip approach to ultralarge systems. A comprehensive review of this transition from the standpoint of packaging, thermal management, and system integration is presented in this article. The benefits and challenges of wafer‐scale integration are discussed. Silicon interconnect fabric, a promising platform for high‐performance heterogeneous wafer‐scale integration, is introduced.

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Power Delivery for High-Performance Microprocessors—Challenges, Solutions, and Future Trends

Cited by 69 publications

References 31 publications

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers

Materials for heterogeneous integration

Wafer‐Scale Integration

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