Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors

Al-Obaidy, Furat; Asad, Arghavan; Mohammadi, Fazel

doi:10.1109/ccece.2019.8861762

Cited by 6 publications

(9 citation statements)

References 11 publications

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“…In comparison to [48,49], the proposed ML model does not require on significant statistical assumptions or mathematical simplifications. Furthermore, when compared to current studies [32,37,38,41,45,46,47], the predicted ANN model has improved accuracy and performance as well. Appendix-E presents an example of a histogram response for given dataset distribution, and feature distribution, with respect to target label.…”

Section: ) Prediction Evaluationmentioning

confidence: 76%

“…The results showed that the proposed approach improved the performance by 5.9%, although the prediction accuracy reached up to 75%, on average, against SRAM design. The architecture of 3D caches linked to multicore power management was used in [47][48][49]. In [47], Furat et al evaluated cache activity to specify power-off opportunities dependent on spatial proximity, with prediction accuracy of 66%, with improved performance of 5%.…”

Section: Power Management For the Memory Systemsmentioning

confidence: 99%

“…The architecture of 3D caches linked to multicore power management was used in [47][48][49]. In [47], Furat et al evaluated cache activity to specify power-off opportunities dependent on spatial proximity, with prediction accuracy of 66%, with improved performance of 5%. The method determined the workload rate, and usability of SRAM and STT-RAM during real-time operation; subsequently, turn-on or turn-off policies were applied to reconfigure memory.…”

Section: Power Management For the Memory Systemsmentioning

confidence: 99%

“…STT-RAM is a likely candidate to replace SRAM and DRAM technologies within the next few years, due to its low leakage current, increased dancer, and high endurance[13]. In the memory…”

mentioning

confidence: 99%

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Power-aware Future Computing Systems Using Machine Learning Techniques

Al-Obaidy

2024

Preprint

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<p>There is a growing demand for hardware systems that are computationally efficient and energy saving, to accelerate compute-intensive applications. These exciting challenges, such as memory access and GPU throughput, take performance, power, and resource trade-offs into account. This is especially relevant to a relatively new approach: Accelerating and running parallel computing systems using a machine learning (ML) technique. The objective of this thesis is to explore the hardware design requirements, and select appropriate choices for multi-core architectures, based on different ML, to address these challenges. This thesis contributes by developing effective hardware architectures which trade-off design objectives, by focusing on the following four distinct fields: • Utilization of low-power cache designs. The objective of this design is to use the artificial neural network (ANN) predictive model to optimize a hybrid spin-torque transfer random-access memory (STT-RAM), and static random-access memory (SRAM), for multicore chips. The simulation results demonstrate that the approach can result in significant power-aware improvement for different workloads. • Development of algorithms that facilitate power savings for three-dimensional integrated networks-on-chips (3D-NoCs) design. A novel approach was efficiently developed to predict the suitable routing algorithm based on the ANN model. A trade-off power-performance function was extracted as a target for the prediction mechanism. The obtained results show high throughput with low power consumption, and reduced thermal hotspots. • Enhance power-aware resources for general purpose graphics processing unit (GPGPU). The customized model is obtained by utilizing the available chip units for each application. The energy-delay product was adopted as the target factor for the proposed ANN model. The results show that when the GPU platform is tuned to the required resources, prediction accuracy, and power consumption are highly improved. This methodology provides more flexibility for the running application to face power challenges when using maximum hardware on the GPU systems. • To improve the performance of the 3D-NoC accelerator platform, we extended the integrated 3D-NoC based ANN simulator to support interconnection routing through adding torus topology. The simulation results for the case study concluded that the modified platform contributes towards low latency and reduced power consumption, especially with respect to high NoC dimensions.</p>

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Section: ) Prediction Evaluationmentioning

confidence: 76%

Section: Power Management For the Memory Systemsmentioning

confidence: 99%

Section: Power Management For the Memory Systemsmentioning

confidence: 99%

“…STT-RAM is a likely candidate to replace SRAM and DRAM technologies within the next few years, due to its low leakage current, increased dancer, and high endurance[13]. In the memory…”

mentioning

confidence: 99%

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Power-aware Future Computing Systems Using Machine Learning Techniques

Al-Obaidy

2024

Preprint

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“…The increased parallelism in LLC has resulted in opting for 3D stacking as compared to the traditional 2D stacking. However, the leakage power is seen to increase greatly due to dense 3D integration [14]. A novel hybrid reconfigurable architecture for LLC is proposed.…”

Section: Literature Reviewmentioning

confidence: 99%

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

Fadnavis¹,

B.S²

2021

IJATEE

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The large-scale growth of the electronics industry in the past decade has led to small-sized gadgets flooding the market. Initially, only Personal Computers (PC) employed the use of multi-core processing, however, now even small hand-held gadgets have come to possess similar computational power as the PC and laptop. With mobile manufacturers opting for multicore processing and graphics -intensive application usage, memory storage and access has become a crucial aspect to achieve high performance.

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