Power modeling for Phytium FT-2000+/64 multi-core architecture

Abstract

Power and energy consumption is the first-class constraint on high-performance-computing (HPC) systems. Understanding the power consumption on such systems is crucial for software optimization and hardware architecture design. Unfortunately, the subtle interactions between the CPU and the memory subsystem make precise power modeling highly challenging on emerging multi-core architectures. This paper presents the first software-based power model for Phytium FT-2000+/64, an ARM-based HPC multi-core architecture. It shows by carefully choosing and modeling a set of systemwide metrics, one can build an accurate power model for the multi-core CPU and the DRAM memory subsystem, two major energy consumers of an HPC system computing node. We evaluate our approach by applying it to HPCC benchmarks and comparing our results against real power measurement. Experimental results show that our approach is highly accurately in modeling power consumption of FT-2000+/64. The average error rate for CPU power modeling in all the scales (8, 16, 32, 64 processes) is 2%, and the average error rate for memory power modeling is about 7.5%. CCS Concepts. • Hardware → Power estimation and optimization.