Practical performance/power alternatives within an existing CMOS technology generation

Abstract

The tremendous demand for advanced microprocessors is making developers offer a superior product at a competitive price which meets specific performance, power, and reliability requirements. Today's products are designed and built with essentially the same design, fabrication, and test tools used by all industry manufacturers and are constrained by the same device physics, package impedance, heat dissipation capability, and battery energy density limitations. In addition, the current technology generation presents a new set of difficult challenges for the treatment of power dissipation.Lowering voltage to reduce power diminishes FET overdrive and the performance of the device. Recapturing performance by migrating quickly to the next scaled technology generation, however, makes low-power designs expensive, and is not always necessary. Standard full scaling preserves physical and electrical relationships between parameters. On the other hand, selective scaling of specific device parameters may allow the exploitation of existing tools and designs by the use of a different design point on the process "surface." This paper describes recent attempts to explore the feasibility of selective scaling and anticipated constraints associated with future technology generations. SELECTIVE SCALINGConventional CMOS concepts of scaling vertical and horizontal device dimensions and the power supply voltage (Vdd), by a common factor are well documented 111. With the exception of Vdd and threshold voltage (VJ, the principles of MOS scaling have historically been practiced by the industry through several technology generations. Efforts to obtain decreases in Vt with technology scaling, however, have been limited. Subthreshold (leakage) current in MOSFETs is due to weak inversion carriers, whose population density is proportional to the Boltzmann factor, e**-(phi)sub-s/kT, where k, T and @hi)sub-s are Boltzmann's constant, the temperature (absolute) and the silicon surface potential, respectively. Since (phi)sub-s is proportional to (V,-VJ. decreasing Vt leads to exponentially increasing leakage current, thereby limiting the amount of Vt reduction possible. Long-lasting power supply voltage standards, such as the 5V standard, have discouraged the scaling of system-level power supplies. Additionally, high-performance circuit design requirements have limited the allowable reduction in device drive, Vdd-Vt, and will continue to dlo so [2].As an alternative to full scaling, selective scaling exploits existing tool capabilities by finding new device operating poilnts within the process tool window which are acceptable for the application. These alternate process settings allolw operation at reduced voltages, thereby mitigating heat dissipation and battery life issues. Generally, specific device parameters may be identified which require the next generation of process tooling to be improved substantially, and so are ineligible to for selective scaling. These parameters include device length tolerance control, oveirlay/alignment control, imag...