Abstract:Downscaling threatens the designers invested in integrity and error mitigation against soft errors. This study formulated the probability of soft error changing the logic state of a Differential Logic with an Inverter Latch (DIL). Using Cadence Virtuoso, current pulses were injected into various nodes in stages until a logic flip was instigated. The voltage and temperature parameters were increased to observe the current level changes over time. The critical charge from each stage was obtained, and a method to… Show more
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