Programmable FSM based built-in-self-test for memory

Maneshinde, Natraj; Hegade, Prateek; Mittal, Rajiv; Palecha, Namita; Suma, M S

doi:10.1109/rteict.2016.7807811

Cited by 4 publications

(1 citation statement)

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“…However, there needs to be a provision to select a few for usage, like debugging. Implementations in [59], [60], and [34] implement multiple algorithms but provide control to select one for execution…”

Section: Mbist Controller With Configurable Algorithmsmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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Section: Mbist Controller With Configurable Algorithmsmentioning

confidence: 99%