Programme and retention characteristics of SONOS memory arrays with layered tunnel barrier

Abstract

Layered tunnel barriers (T-ONO) might help circumvent retention limitations of nitride charge trapping devices (SONOS) programmed/erased by direct tunnelling without invoking high-K dielectrics in the gate stack. In order to establish to what extent the properties of a T-ONO tunnel layer influence the performance of SONOS memories, NOR memory arrays containing a silicon oxide/silicon nitride/silicon oxide T-ONO layer, a silicon nitride charge trapping layer and a silicon oxide blocking layer were fabricated and investigated. The T-ONO layer was formed using wet reoxidation of the silicon nitride, as this process is known to generate a lot of traps at the interface between silicon nitride and silicon oxide, as well as in the reoxidized portion of the silicon nitride itself. Besides standard memory measurements like programme/erase behaviour, endurance and retention, charge centroid extraction measurements were carried out in order to explain the retention behaviour and associate it with the position of the charge. It has been demonstrated that the performance of SONOS memories with a T-ONO layer strongly depends on the technological properties/quality of the T-ONO barrier which, therefore, may not be a universal solution to retention problems in SONOS devices.

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