Property analysis and design understanding

Kuhne,; Grosse,; Drechsler, Rolf

doi:10.1109/date.2009.5090855

Cited by 6 publications

(8 citation statements)

References 21 publications

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“…The resulting BDD S = ¬E is shown in Figure 1 Note that the sufficient antecedents can also be constructed by computing all minimal unsatisfiable subformulas [12] of the inital property. This relation is further discussed in [1].…”

Section: Property Analysismentioning

confidence: 84%

“…In order to decrease the overhead of formal methods, techniques to aid the verification engineer in design understanding and to ease the formalization of the specification have been introduced in [1]. The first method automatically analyzes a given property, identifying too strong constraints on the environment or the internal state of the DUV.…”

Section: Introductionmentioning

confidence: 99%

“…The work is concluded in Section VII. A discussion of the presented techniques and of related work can be found in [1].…”

Section: Introductionmentioning

confidence: 99%

“…Formalizing a specification as a set of properties is a tedious and time consuming process. In this paper, we show the application of techniques to aid the verification engineer in writing properties in a qualitydriven BMC flow, that have been introduced in [1]. The first method can be used to remove redundant assumptions from properties and to separate different scenarios.…”

mentioning

confidence: 99%

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Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow

Kühne

Große

Drechsler

2008

2008 Ninth International Workshop on Microprocessor Test and Verification

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Abstract-In the design process of digital systems, functional verification is a major issue. Generally, formal methods like bounded model checking (BMC) offer the highest quality of the verification results, especially when used in combination with techniques that check if a set of properties forms a complete specification of a design. However, in contrast to simulationbased methods, like random testing, formal verification requires a detailed knowledge of the design implementation. Formalizing a specification as a set of properties is a tedious and time consuming process. In this paper, we show the application of techniques to aid the verification engineer in writing properties in a qualitydriven BMC flow, that have been introduced in [1]. The first method can be used to remove redundant assumptions from properties and to separate different scenarios. The second technique, here called inverse property checking, takes an expected behavior of a design and automatically generates valid properties that can be checked for conformance with a specification. Both techniques can serve to reduce the number of iterations to obtain full coverage, when integrated with the verification flow. The benefits of the techniques are demonstrated with a memory management unit.

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Section: Property Analysismentioning

confidence: 84%

Section: Introductionmentioning

confidence: 99%

“…The work is concluded in Section VII. A discussion of the presented techniques and of related work can be found in [1].…”

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow

Kühne

Große

Drechsler

2008

2008 Ninth International Workshop on Microprocessor Test and Verification

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“…In [24] an approach to understand the reasons for contradictions in the antecedent of a property has been proposed. As described in [25], properties can be strengthened automatically and in case of a failing coverage check, suggestions are made how to complete the set of properties.…”

Section: Coverage and Property Analysismentioning

confidence: 99%

WoLFram- A Word Level Framework for Formal Verification

Sülflow

Kühne

Fey

et al. 2009

2009 IEEE/IFIP International Symposium on Rapid System Prototyping

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Due to high computational costs of formal verification on pure Boolean level, proof techniques on the word level, like Satisfiability Modulo Theories (SMT), were proposed. Verification methods originally based on Boolean satisfiability (SAT) can directly benefit from this progress.In this work we present the word level framework WoLFram that enables the development of applications for formal verification of systems independent of the underlying proof technique. The framework is partitioned into an application layer, a core engine and a back-end layer. A wide range of applications is implemented, e.g. equivalence and property checking including algorithms for coverage/property analysis, debugging and robustness checking. The backend supports Boolean as well as word level techniques, like SMT and Constraint Solving (CSP). This makes WoLFram a stable backbone for the development and quick evaluation of emerging verification techniques.

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An Abstraction-Refinement Framework for Trigger Querying

Avni

Kupferman

2011

Static Analysis

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Abstract. Trigger querying is the problem of finding, given a system M and an LTL formula ϕ, the set of scenarios that trigger ϕ in M ; that is, the language L of finite computations of M such that all infinite computations that have a prefix in L continue with a suffix that satisfies ϕ. For example, the trigger query M |=? → F err asks for the set of scenarios after which err aught to eventually happen. Trigger querying thus significantly extends query checking, which seeks propositional solutions, and is an extremely useful methodology for system exploration and understanding. The weakness of trigger querying lies in the fact that the size of the solution is linear in the size of the system. For trigger querying to become feasible in practice, we must offer solutions to cope with systems of big, and possibly infinite, state spaces. In this paper we describe an abstraction-refinement framework for trigger querying. The general idea is to replace the reasoning about M by reasoning about an abstraction MA of M , and return to the user two languages, L l and Lu, that under-and over-approximate L, respectively. We consider predicate abstraction, and the languages L l and Lu are defined with respect to the set of predicates. The challenge in defining the approximating languages is that trigger querying does not have a clear polarity, and the definition of L l and Lu has to combine the upper-and over-approximations of M . We describe an automata-theoretic approach for refining and reducing Lu \ L l . While refinement for model checking is lengthwise, in the sense that it is based on counterexamples, here we suggest both lengthwise and widthwise refinement, where the latter is based on cuts in an automaton for Lu \ L l and thus can symbolically handle batches of counterexamples. We show that our framework is robust and can be applied also for classical query checking as well as variants and extensions of trigger querying.

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Property analysis and design understanding

Cited by 6 publications

References 21 publications

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow

WoLFram- A Word Level Framework for Formal Verification

An Abstraction-Refinement Framework for Trigger Querying

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