Proposal for a Spin Logic Device Based on Magneto-Electric Effect and Spin Hall Effect

Wang, Sen; Zhang, Xue; Li, Henan; Shan, Dan; Fan, Hongliang

doi:10.2139/ssrn.4130144

Cited by 1 publication

(1 citation statement)

References 28 publications

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“…In particular, ASL does not require additional hardware for repeated spin-charge conversion, which has attracted considerable attention [11][12][13][14][15][16][17][18]. Various types of logic circuits based on ASL have been proposed, such as full adder [19], D flip-flop [20], RS flip-flop [21], and XOR gate [22].…”

Section: Introductionmentioning

confidence: 99%

Proposal of a 2-4 Decoder Based on All-spin Logic and Magnetic Tunnel Junction

Wang,

Zhang,

Shan

2024

Preprint

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A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The proposed 2–4 decoder employs 5-input minority gates and single-input single-fan-out (SISF) structure. Meanwhile, the inverters are eliminated by initializing the magnetization of the MTJ fixed layer in different directions to realize the inputs of the original or inverse variables. To ensure that the proposed 2–4 decoder works properly, an asynchronous clock scheme is proposed, which divides the input signal into three phases and the operating voltage into two phases in one clock cycle. The operation of the proposed decoder is validated by the magnetization dynamics/spin transport self-consistent simulation framework, and the simulation results show that the delay and energy dissipation of the decoder are at the level of nanosecond and femtojoule, respectively. In addition, to illustrate the advantages of the 5-input minority gate, inverter-free structure, and SISF structures in the design of the proposed 2–4 decoder, a second 2–4 decoder is proposed using 3-input minority gates, inverters, and single-input multiple-fan-out structure. Compared with the second decoder, the layout area of the first decoder is reduced to 37.9%, the total channel length is reduced to 40.8%, the number of clock cycles is reduced to 1/3, and the energy dissipation is reduced by at least 3 orders of magnitude. Importantly, the design methods used in this work, such as multi-input minority gates, SISF structure, and inverter-free structure, provide an interesting approach for designing large-scale ASL logic circuits.

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