Proposal of a declarative and parallelizable artificial neural network using the notification-oriented paradigm

Schütz, F.; Fabro, João Alberto; Ronszcka, Adriano F.; Stadzisz, Paulo Cézar; Simão, Jean Marcelo

doi:10.1007/s00521-018-3517-y

Cited by 4 publications

(2 citation statements)

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“…Em trabalhos de Schütz [23] apresentou-se uma solução alternativa de Rede Neural Artificial (RNA) via Tecnologia LingPON, chamada de NeuroPON [24]. A NeuroPON foi usada para RNA do tipo Multilayer Perceptron para funções XOR e Iris Dataset, ambas com treinamento pelo método de backpropagation.…”

Section: Trabalhos Prévios Em Pon-hd E Tecnologia Pon-unclassified

The Notification Oriented Paradigm Language to Digital Hardware as an Intuitive High-level Synthesis Tool

Kerschbaumer

Kaviatkovski

Garcia

et al. 2021

RITA

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The parallelism allowed by FPGAs has attracted attention for knowing applications that need processing power. However, the need for specific and very technical development language has not stimulate its broad use. As an alternative, there are High-level Synthesis Languages (HSL), which allow less complicated FPGA use. However, they do not tend to take full advantage of the FPGA technology. Therefore, another alternative was developed, based on the Notification Oriented Paradigm (NOP), called NOP for Digital Hardware (NOP-DH). NOP allows development in high level with its rule-oriented language called NOPL. Its entity decoupling, parallelism, and redundancy avoidance are useful for best performance. In turn, the NOP-DH brings NOP for the FPGA context with the benefits observed in software but enhanced by hardware nature. This paper reviews the NOPL for NOP-DH (NOPL-DH) that aims high level programming for FPGA. The paper proposes the NOPL-DH test by independent developers, by developing a monitoring device for a box transporting bidirectional conveyer. As a result, NOPL-DH allowed high-level development under the NOP-DH structure in an FPGA, without the need for technical knowledge and, still, maintaining and exploring the NOP properties in FPGA

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Section: Trabalhos Prévios Em Pon-hd E Tecnologia Pon-unclassified

The Notification Oriented Paradigm Language to Digital Hardware as an Intuitive High-level Synthesis Tool

Kerschbaumer

Kaviatkovski

Garcia

et al. 2021

RITA

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“…The NOP solutions have been experimented to improve performance and even parallelism/distribution in the usual von Neumann-based platforms, both mono and multi-core ones [10], [14]. However, such platforms cannot fully achieve NOP benefits.…”

Section: Introductionmentioning

confidence: 99%

NOCA — A Notification-Oriented Computer Architecture: Prototype and Simulator

Linhares¹,

Pordeus

Simão³

et al. 2020

IEEE Access

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The Notification Oriented Paradigm (NOP) introduced a new organization of software and hardware logic based on notifications among computational entities. This NOP new organization avoids processing redundancy and allows processing unit decoupling, therefore permitting proper processing performance and processing parallelism/distribution. Thus, the NOP provides means to make efficient use of the parallel execution capabilities of modern computing systems. However, as expected, the execution dynamics of NOP, based on notifications, is not efficiently performed by the hardware of most current computing systems. This paper presents a new solution called Notification-Oriented Computer Architecture (NOCA), which is suitable for the execution of software developed according to the NOP computing model. The NOCA was designed according to principles of generality and scalability, which allow it to execute NOP software of any size by fetching the application from memory. The proposed architecture is organized as a fine-grained multiprocessor that hierarchically executes instructions through sets of specialized processing cores. Preliminary experiments performed on prototypal FPGA implementation of the NOCA showed the expected behavior of executing NOP applications according to its theoretical computing model. This paper also presents experiments performed on a NOCA simulator extending the scale of parallelization of applications. Results show improvements in maximizing the speedups at higher scales of parallelization, as well as minimizing the effects of processor-to-memory communication bottlenecks by reducing the number of required memory accesses during execution.

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