Pt/PZT/n-SrTiO₃ Ferroelectric Memory Diode

Abstract

We fabricated a new nonvolatile ferroelectric memory, which consists of vertical metal-ferroelectric- semiconductor diodes. Our diode has a simpler structure than an Ferroelectric Random Access Memory (FRAM) cell, and operates at a lower voltage than Metal Ferroelectric Semiconductor Field Effect Transistors (MFS-FETs) or conventional flash memories. We demonstrated the memory operation using a Pt/PZT/n- SrTiO3 diode in this work. We deposited (001)-oriented PZT on (100) 0.5 wt% Nb doped n-type SrTiO3 substrate using a laser ablation technique. The diodes had a hysteresis loop in their capacitance-voltage characteristics due to ferroelectric polarization in the PZT layer. Their current-voltage curves were Schottky-diode-like and also had a hysteresis loop due to the ferroelectric remanent polarization. We confirmed correct nonvolatile and nondestructive memory readout operation. The write voltages were -5 V to write a logic “0” and above 2.5 V to write a logic “1”. The read voltage was 0.8 V.

Method to distinguish ferroelectric from nonferroelectric origin in case of resistive switching in ferroelectric capacitors

“…[20][21][22][23][24][25][26][27][28] In the case of ferroelectrics, the issue is further complicated by characteristics such as interface properties, i.e., the barrier height and the sign of the remnant charge of the ferroelectric material. [20][21][22][23]27,28 Nonetheless, from I-V characteristics alone it might be a risky task to conclude the nature of the underlying mechanism. 19,26,28,30 Therefore, it is critical to be able to distinguish a ferroelectric switching from that of a nonferroelectric origin, and this forms the motivation for this letter.…”

Resistive Switching Behavior in Ferroelectric Heterostructures

“…Thus, they not only experimentally demonstrated the RS behavior in ferroelectric diodes but also inferred that the RS behavior in ferroelectric heterostructures is polarization dependent. Subsequently, the RS behaviors in BaTiO 3 /Nb:SrTiO 3 , BiFeO 3 /SrRuO 3 , (PbLa)(ZrTi)O 3 /LaNiO 3 , and other ferroelectric heterostructures were also reported, and the possible mechanisms were discussed . Using p‐type semiconductor (PbLa)(ZrTi)O 3 as a ferroelectric layer and p‐type semiconductors (LaSr) 2 CuO 4 or LaNiO 3 or n‐type semiconductors (NdCe) 2 CuO 4 or Sr(TiNb)O 3 as a substrate electrode, p–p and p–n ferroelectric heterojunctions were fabricated.…”

“…Using p‐type semiconductor (PbLa)(ZrTi)O 3 as a ferroelectric layer and p‐type semiconductors (LaSr) 2 CuO 4 or LaNiO 3 or n‐type semiconductors (NdCe) 2 CuO 4 or Sr(TiNb)O 3 as a substrate electrode, p–p and p–n ferroelectric heterojunctions were fabricated. [27b] The results showed that RS behavior was observed in p–n heterostructures with an ON/OFF ratio of 300 but not in p–p heterostructures. By analyzing the conduction mechanism in the p–p or p–n heterostructures, it has been suggested that the interfacial energy band structures of these heterostructures modulated by polarization switching determine the RS behavior in ferroelectric heterostructures.…”

1-D simulation of a novel nonvolatile resistive random access memory device

“…However, the ongoing trend of miniaturization may level the technological efforts in bringing FRAM into production, since charge-based devices require a minimum area for information readout. Various concepts of resistive memories (RRAM)-e.g., based on magnetic tunnel junctions-(MRAM) [4], phase change materials (PCM, Ovonics) [5], [6], ferroelectric tunnel junctions [7], ferroelectric field-effect transistors (FerroFET) [8], [9], ferroelectric diodes [10]- [12], or charge trapping/detrapping effects [13], which do not show this disadvantage, are currently under development. The key issue of all approaches is to overcome the limitations of today's flash memories concerning low writing speed, cycling endurance, and large programming voltages.…”

“…Meyer between two ohmic contacts. The metal-ferroelectricsemiconductor-metal (MFSM) structure can be regarded as a generalization of existing ferroelectric diode concepts consisting of a one-layer structure, in which the ferroelectric layer is embedded in two metal electrodes (MFM structure) or sandwiched between a metal and a semiconductor (MFS structure) [10]- [12]. The new device combines the ferroelectric information storage principle with a lowresistive information readout.…”