Quad-Rail Sense-Amplifier Based NoC Router Design

2022

JECNAM

Reducing the power consumption in a VLSI circuits is a prime concern now a days. Memory circuits play an important role in the design of electronic small power devices. Almost every digital systems is having memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper conventional SRAM cell is modified little bit to reduce the dynamic power dissipation. The overall capacitance reduced by adding few extra transistors. Because of the fact that charging and the discharging of the bit lines consumes the most power , so 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. In this paper 6T SRAM cell as well as 8T SRAM cell simulated and their performance compared in terms of power dissipation.

Section: Ram Design Conventional 6t Sram Cellmentioning

confidence: 99%

“…A traditional SRAM cell uses six transistors for reading and writing. It has the advantage of small footprint [9][10][11][12]. Here, reading and writing are done through a single bit line [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

6T and 8T SRAM Cell Simulation with Power Loss Analysis

2022

JECNAM

“…change the status from "0" to "1" after reading a little cell or vice versa) or writing errors (i.e., writing to the data bit cell fails to overwrite the previously saved value). Some supporting devices such as single-end sensor cells are installed [4]- [8] and difference sensor cells [9], [10] to solve these problems. A new cell of SRAM was proposed.…”

Section: Proposed Dual Vth Scheme Effect On Srammentioning

confidence: 99%

Enhancing Energy Efficiency of Sram through Optimization of Sram Array Structures

2022

JECNAM

Reliability is a major concern in the microprocessor industry. In terms of power consumption, SRAM plays a key role in improving processing performance. Improving SRAM efficiency requires changes to the array structure. A general method in which the SRAM array has more rows than columns.The above techniques are proposed to improve efficiency by 10% for 8kbit and 40% for 64kbit at the same SRAM byte density and supply voltage. Implement suggested deep submicron technology for better reliability. Many proposed designs focus on low power consumption, often with reduced response times.As the technology scales, the power consumption of on-chain system devices with gate leakage, subthreshold current, and tunneling increases significantly. Small SRAM capabilities are important.This task demonstrates the potential of using larger SRAM array structures to achieve better SRAM energy efficiency, especially when the number of rows is less than the number of low-power columns. Compared to traditional 8T SRAM, the proposed 10T cell uses less power, has a different temperature and better performance.

“…Architectural transformations can be performed to trade off one constraint against another, such as the speed domain. Concrete solutions that help reduce the arithmetic complexity of the algorithm can be found in [9] to address speed, area, and power complexity. All in all, multipliers are the essential segments of cryptography frameworks like elliptic bend cryptography calculations and advanced sign handling calculations like quick Fourier change (FFT) [10].…”

Section: Introductionmentioning

confidence: 99%

Modified Efficient OMS LUT Design for Memory-Based Multiplication

2022

JAIMLNN

This paper proposes an efficient LUT (Look-Up-Table) design called Efficient EOMS (Efficient-OMS Design) for memory-based operations. This proposed design can be used for FPGA implementation as well as ASIC. The proposed design is a better choice than ordinary OMS (Odd Multiplier Store) and is preferred in many DSP calculations where one of the inputs to the filter coefficients is fixed. In this design (N+1), the possible product terms of the input multiplicands with fixed coefficients are stored directly in memory. Doing so allows for a simpler and faster design, unlike the previous proposal OMS (Odd Multiple Storage).Designs that extract odd multiples of the product term can significantly reduce path delay and area complexity with very simple control circuitry. Using (N+1) technology can significantly reduce the area compared to ordinary OMS technology. Additionally, the EOMS technical design is coded in Verilog and simulated and synthesized using Xilinx tools.