Quantitative monitoring of STL with edit distance

Abstract

In cyber-physical systems (CPS), physical behaviors are typically controlled by digital hardware. As a consequence, continuous behaviors are discretized by sampling and quantization prior to their processing. Quantifying the similarity between CPS behaviors and their specification is an important ingredient in evaluating correctness and quality of such systems. We propose a novel procedure for measuring robustness between digitized CPS signals and signal temporal logic (STL) specifications. We first equip STL with quantitative semantics based on the weighted edit distance, a metric that quantifies both space and time mismatches between digitized CPS behaviors. We then develop a dynamic programming algorithm for computing the robustness degree between digitized signals and STL specifications. In order to promote hardware-based monitors we implemented our approach in FPGA. We evaluated it on automotive benchmarks defined by research community, and also on realistic data obtained from magnetic sensor used in modern cars.

Generating automated and online test oracles for Simulink models with continuous and uncertain behaviors

“…Thus, as shown by Dokhachi et al [33], the time overhead of their approach is considerably high as the time history grows. Jakšić et al [43] recently developed an online monitoring procedure for STL by translating STL into automata monitors with a complexity that is exponential in the size of the formula. In contrast to our work, such monitors are not able to handle continuous signals sampled at a variable rate directly.…”

Introduction to the special issue on runtime verification

“…Jakšić et al [32] monitor the physical behavior of cyber-physical systems. They provide a quantitative semantics of Signal Temporal Logic by introducing a weighted edit distance.…”

Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems

“…However, a lot of training is required in order to identify specific system behaviour. Extending the system by an external FPGA-based device using peripheral buses [25] seems more realistic, although it comes with the restriction that only the external communication on [15] n / a -n / a P2V [19] cust. HidICE [5] cust.…”

“…While many of these approaches have the merit of unbounded online evaluation, they are inconvenient in an iterative development or testing process because the properties to be evaluated are synthesised directly to programmable logic which is extremely time-consuming. The same applies to the monitor construction presented in [15]. A solution that allows for a rapidly adjustable evaluation of past-time MTL properties is given in [24].…”