Quantum-Dot Cellular Automata Technology for High-Speed High-Data-Rate Networks

Hariprasad, Adepu; Ijjada, Sreenivasa Rao

doi:10.1007/s00034-019-01119-9

Cited by 6 publications

(3 citation statements)

References 21 publications

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“…Figure 2 displays this gate. If the majority gate inputs are shown by A, B, and C, the output of this gate is denoted as follows [2,8]:…”

Section: Qca Gatesmentioning

confidence: 99%

“…Additionally, if the constant values "1" and "0" are assigned to the input C, the MG will function as AND gate and OR gate, respectively [2,8].…”

Section: Qca Gatesmentioning

confidence: 99%

“…The CMOS technology is a dominate technology for digital circuits design, but this technology has several concerns at nano-scale including short channel effects. The Quantumdot Cellular Automata (QCA) technology is a significant kind of nanotechnology for the implementation of digital circuits such as full adder, comparator, shift register, counter, multiplier, and memory [1][2][3][4][5][6][7][8]. This kind of nanotechnology has significantly low delay and area compared to CMOS technology [3,9].…”

Section: Introductionmentioning

confidence: 99%

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Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

2021

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Quantum-dot cellular automata (QCA) technology is a kind of nanotechnology utilized for building computational circuits. It can be a good technology for overcome CMOS drawbacks at nano-scale due to its low delay and area. The Content-Addressable Memory (CAM) is a very fast memory that can perform search operations in a very short time. This feature makes the relative popularity of these memories and many applications for them, especially in network routing and processors. In this study, a novel loop-based circuit is designed for the QCA memory unit, which reduces area, cell count, latency, and cost. The obtained results using QCADesigner tool version 2.0.3 demonstrate that the designed QCA memory unit utilizes 16 cells, 0.01 µm2 area, and 0.25 clock cycles and has a reduction of 33% in the number of cells, 50% in area, 50% in latency, and 75% in cost compared to existing works. Then, this memory unit is utilized to design an efficient structure for CAM circuit. The results show that the developed structure for CAM circuit has 0.75 clock cycles, 32 cells, and 0.03 µm2 area, and it has a reduction of 20% in the number of cells, 25% in area, 40% in latency, and 75% in cost compared to existing works.

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“…Figure 2 displays this gate. If the majority gate inputs are shown by A, B, and C, the output of this gate is denoted as follows [2,8]:…”

Section: Qca Gatesmentioning

confidence: 99%

“…Additionally, if the constant values "1" and "0" are assigned to the input C, the MG will function as AND gate and OR gate, respectively [2,8].…”

Section: Qca Gatesmentioning

confidence: 99%