“…The variables used in forming an address for a Q-vector of the functionality can be combined into a single node, with showing all the identificators of lines, which form vector-address. The register graph of the combinational circuit is ranked by levels of formation of input signals, enabling conditions for concurrent handling of the elements of the same level and performability of Seidel iterations [2], which improve the performance of algorithms for fault-free simulating digital systems. The structure, represented in Fig 3b, is interesting by its register implementation that can be used to formalize the descriptions of both software and hardware models of gate, registry and system levels.…”