Quaternary Logic Lookup Table in Standard CMOS

Brito, Diogo; Rabuske, Taimur; Fernandes, Jorge; Flores, Paulo; Monteiro, José

doi:10.1109/tvlsi.2014.2308302

Cited by 19 publications

(12 citation statements)

References 14 publications

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“…According to paper [13] present a full adder prototype based on the designed LUT, fictitious in a standard 130-nm CMOS technology, able to work at 100 MHz while overriding 122 μW. The experimental results express the correct quaternary operation and confirm the power efficiency of the proposed design.…”

Section: Related Workmentioning

confidence: 77%

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

2018

Teh. vjesn.

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In the recent years, there were major importance to Multiple Valued Logic (MVL), where the most common reasons for considering the implementation of MVL circuits better then binary valued circuits are that reducing wiring congestion as compared to binary circuits, using a single conductor to transmit three or more discrete voltage or current values allows for greater information content per wire and the circuit cost models would be more economical. Therefore, in this paper the MVL concepts have been used to design 4-bit quaternary MVL Arithmetic and Logic Unit, which is considered a basic unit of a MVL microprocessor. It is the "heart" of a microprocessor and we could say that everything else in the microprocessor is there to support the ALU. The proposed Arithmetic and Logic Unit will do the operations as Addition, Subtraction, Maximum, Minimum and Invert. Simulation Program with Integrated Circuit Emphasis (SPICE) tool in Cadence simulator used in simulation the proposed Arithmetic and Logic Unit. The simulation results tells that the design is more efficient compared with the binary ALU and the circuit will be less area and less number of transistors.

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Section: Related Workmentioning

confidence: 77%

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

2018

Teh. vjesn.

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“…The high and low resistance values of ReRAM crossbars ( and ) are adopted from [3]. We utilize the design from [2] to implement the and ℎ look-up tables in the hybird design. A modified design of [7] is used as the CMOS baseline of design.…”

Section: Evaluation 51 Experiments Setup and Benchmarkmentioning

confidence: 99%

ReTransformer

Yang

Yan

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…In Traditional binary CMOS advanced circuits, static power utilization has its linkage to outflow current, and dynamic power consumption is given by equation 1 given underneath (1), where C is the capacitance of the node being determined and VDD is the power supply voltage…”

Section: Introductionmentioning

confidence: 99%

“…This capacitance C includes the directing capacitance of interfacing wires as well. It has been stated that routing overstep transistors impact for latency and power dissipation of design in current CMOS forms [1]. This becomes quite critical in FPGA'S where the power where the power used in directing may reach up to 70% of general utilization [2].…”

Section: Introductionmentioning

confidence: 99%

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Design of Lookup Table using Quaternary Logic in Voltage Mode Standard CMOS Circuit

S.Jadhav¹

2018

Helix

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Designer face challenges in interconnection due to the large number of components. Interconnection and power consumption perform significant part in this paper. The shortcomings of the previous work done is high interconnections, which leads to high power usage along with more area required. The Binary logic circuits is constrained by using the number of interconnections, which increases the delay and power consumption with the boom in logic. So we design new techniques that is going to reduce the interconnection of the circuit as well as the power consumptions. Multiple-valued logic can decrease the number of required interconnections. In this paper we use quaternary to binary decoder to reduce the multiplexer control lines is the vital parts of the processing component and therefore it has a focal point of research. Therefore, the design of adders through multiplexer using multi valued logic can show to be very beneficial. So we introduce and full adder based totally at the designed quaternary lookup table.

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Quaternary Logic Lookup Table in Standard CMOS

Cited by 19 publications

References 14 publications

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

ReTransformer

Design of Lookup Table using Quaternary Logic in Voltage Mode Standard CMOS Circuit

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