Radiation Hardness Characterization of a 130nm ASIC Library Technology

Dumitru, Radu; Hafer, C.; Wu, Tzu-Wen; Rominger, Rob; Gardner, Harry; Milliken, Peter; Bruno, Kevin; Farris, T.

doi:10.1109/redw.2010.5619510

Cited by 4 publications

(1 citation statement)

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“…To overcome this limitation, a new design of an ultra-low power and harsh-environment immune voltage reference is performed. We firstly choose to port the design to a more suitable SOI industrial technology with Complementary Metal-Oxide-Semiconductor (CMOS) process node of 130 nm featuring a much reduced gate and buried oxides thickness and hence TID degradation [ 4 ]. Secondly, we improved the architecture by introducing a cascode bias stage for enhanced stability, and a new start-up design to avoid start deficiency at low temperature and extreme corners (resulting in high V th ).…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

Boufouss

Francis

Kilchytska

et al. 2013

Sensors

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This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

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Section: Introductionmentioning

confidence: 99%