Radio-frequency modeling of square-shaped extended source tunneling field-effect transistors

Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer

“…Furthermore, the Shockley-Read-Hall and Auger recombinations; concentration dependent mobility, bandgap narrowing effect, field dependent mobility and trap-assisted tunneling (TAT) models were used to model the recombination and generation in the highly doped regions. Also, we recently presented the validation of our simulation non-local BTBT model by tuning of the effective electron and hole masses as done in our earlier works 13,15,23,35,40 .…”

“…The lower gate to source capacitance in the extended source TFET with 3C-SiC substrate and pocket is due to the barrier width reduction at the source to channel edge. However, due to the inversion layer extension from the drain-side toward the source-side, the dominant capacitance between the gate and the inversion layer under a TFET gate is gate-drain capacitance 25,35 . Figure 9 illustrates the effect of the 3C-SiC substrate and dopant pocket on the channel resistance (R ch ) of a SES TFET with 30 nm gate length versus the gate voltage biased at drain voltage of 0.7 V. It can be seen that the channel resistance value of the SES TFET with 3C-SiC substrate and pocket is much lower than that of the conventional SES TFET due to the high channel conductivity induced the existence of the n-type pocket at the interface of source and channel.…”

“…The channel resistance of the device plays a crucial role in determining transport time delay since R ch ×C gd acts as an index for showing of the channel charges response speed to gate signal 25,35 . The variation in the transport time delay versus the gate voltage for the SES TFET with 3C-SiC substrate and pocket and conventional SES TFET with 30 nm gate length at drain voltage of 0.7 V is shown in Figure 10.…”

“…The RF performances of the SES TFET with 3C-SiC substrate and pocket are considered by extracting the cutoff and maximum oscillation frequencies and are compared with the conventional SES TFET. The cutoff and maximum oscillation frequencies are frequencies at which the current and unilateral power gains of a TFET drops to unity, respectively 25,35 . Figure 11 displays the gate capacitance values of cutoff frequency for the SES TFET with 3C-SiC substrate and pocket and conventional SES TFET with 30 nm gate length as versus the gate voltage biased at drain voltage of 0.7 V. It is observed that the extended source TFET with 3C-SiC substrate and pocket shows better value of cutoff frequency when compared with that of the conventional SES TFET due to its higher transconductance, as shown in Figure 5.…”

“…On the other hand, we recently presented the DC and RF performances of double-gate SES TFETs 35,37 . In this paper, in order to further enhance the device performance, the 3C-SiC substrate and an n-type pocket in the channel at the source edge of SES TFET have been placed and its performance is compared with conventional SES TFET with similar dimensions.…”