Rate Matching and Interleaved Hardware Sharing Design

Huo, Kejia; Hu, Zhuhua; Liu, Dake

doi:10.1109/icece54449.2021.9674248

Cited by 1 publication

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This process ensures efficient utilization of the channel resources and improves transmission reliability Rate-matching and channel interleavers in various wireless standards have been widely discussed in literature. A shared interleaver and rate-matching for turbo codes, LDPC and polar codes is discussed in [14]. Though detailed hardware architecture is not presented, sharing of memory and few modules is proposed.…”

Section: Introductionmentioning

confidence: 99%

A reduced complexity rate-matching and channel interleaver/de-interleaver for 5G NR

J L,

Jayakumari

2024

Eng. Res. Express

View full text Add to dashboard Cite

Rate matching and channel interleavers play a pivotal role in code rate adaptation and minimizing burst errors in communication systems. The data and control channels in the Fifth generation (5G) New Radio (NR) employs distinct channel interleavers/de-interleavers for reducing bit error rate. However, the independent implementation results in a substantial increase in silicon cost. To address this challenge, hardware sharing is pivotal for optimizing resource utilization and improving overall system performance. This study introduces a rate-matching architecture and a simple algorithm for the creation of a new Shared-Resource Channel interleaver/De-interleaver (SRC) architecture. The proposed work ensures low complexity tailored for both data and control channels within the 5G NR framework by incorporating the hardware sharing technique. The proposed SRC architecture, synthesized on the Virtex-7 Field Programmable Gate Array (FPGA), showcases noteworthy advancements over existing 5G NR interleaver architecture, achieving a notable 23% reduction in resource utilization. Through implementation using the Qflow Compiler in 45nm CMOS technology, the ASIC synthesis of the proposed design demonstrates a substantial decrease in hardware complexity and area by 44.6% and 43%, respectively. Furthermore, the proposed architecture exhibits a 19.2% reduction in power consumption compared to its existing counterpart in 5G NR. The proposed integrated design demonstrates a remarkable resource efficiency by occupying nearly half the resources compared to individual implementations

show abstract

Section: Introductionmentioning

confidence: 99%