Real-time 2-D wavelet transform implementation for HDTV compression

Uzun, I.S.; Amira, Abbes

doi:10.1016/j.rti.2005.01.001

Cited by 15 publications

(9 citation statements)

References 16 publications

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“…5(d). Each decomposition level j can be seen as the further decomposition of a 2-D data set I j À 1 (having N jÀ1 Â N jÀ1 samples) into four sub-bands LL j ; LH i ; HL j and HH j (each having N j À 1 /2 samples, where N is input data/samples) [25]. …”

Section: Article In Pressmentioning

confidence: 99%

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Krill¹,

Ahmad²,

Amira³

et al. 2010

Signal Processing: Image Communication

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Section: Article In Pressmentioning

confidence: 99%

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Krill¹,

Ahmad²,

Amira³

et al. 2010

Signal Processing: Image Communication

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“…The application is generally decomposed into elementary units of optimized description and synchronized functioning [18]. A new high-level language, called Handel-C, appeared recently [2,8,11,17,[19][20][21][22][23]. Handel-C is based on the conventional ISO-C language and allows the software design of hardware systems.…”

Section: Architectural Models At the Filter Levelmentioning

confidence: 99%

Design and implementation of optimized architecture for computing the 2D‐DWT for JPEG2000 compression

Souani

Gazzah

Besbes

2009

Circuit Theory & Apps

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SUMMARYTo obtain an effective and efficient system, a multitude of architectural solutions must be assessed and their performances compared. Design and evaluation of several hardware architectures require enormous time for their development and the evaluation. In this paper, an exploration of possible architectures for the 2D-discrete wavelet transform (DWT) is accomplished. Particularly, filters used by the standard JPEG2000 are studied: the lossy 9/7 and the lossless 5/3 filters. The designs have been coded with high description level using Handel-C language and the target hardware is Xilinx FPGA of the Virtex-4 family. It is known that the technique of in-place calculation of the 2D-DWT by lifting scheme allows saving space memory, but the problem is that the computed coefficients are not stored in consecutive addresses, and a system for address decoding becomes necessary. The address decoding must be made at every new decomposition level. We propose then a new simple and efficient technique that allows storing the calculated coefficients in a homogeneous space memory and in consecutive addresses. No additional memory or address decoding is necessary. Finally, the designed system allows a rather high throughput and optimized number of hardware resources.

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“…In the never ending quest for a perfect picture, research in developing fast, high-quality algorithms for processing pictures/videos captured by consumer digital cameras or cell-phone cameras [80] is expected to continue well into the future. Of course, the developments in industrial inspection [25,34,67,135,147] and medical imaging systems [18,23,24,44,136,143,145] will continue to progress. The use of color image data [8,85,107,109], or in some cases, multispectral image data [139] in real-time image/video processing systems is also becoming an important area of research.…”

Section: Growth In Applications Of Real-time Image/video Processingmentioning

confidence: 99%

“…Another example showing the power of an FPGA for accelerating 3D image preprocessing tasks can be found in [145], where the problem of 3D median and convolution filtering for 3D medical image processing was considered. Since software implementations could not meet the real-time constraints, a hardware-based solution using an FPGA was considered.…”

Section: Image Filtering Operationsmentioning

confidence: 99%

Real-Time Image and Video Processing: From Research to Reality

Kehtarnavaz¹,

Gamadia²

2006

Synthesis Lectures on Image, Video, and Multimedia Processing

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This book presents an overview of the guidelines and strategies for transitioning an image or video processing algorithm from a research environment into a real-time constrained environment. Such guidelines and strategies are scattered in the literature of various disciplines including image processing, computer engineering, and software engineering, and thus have not previously appeared in one place. By bringing these strategies into one place, the book is intended to serve the greater community of researchers, practicing engineers, industrial professionals, who are interested in taking an image or video processing algorithm from a research environment to an actual real-time implementation on a resource constrained hardware platform. These strategies consist of algorithm simplifications, hardware architectures, and software methods. Throughout the book, carefully selected representative examples from the literature are presented to illustrate the discussed concepts. After reading the book, the readers are exposed to a wide variety of techniques and tools, which they can then employ for designing a real-time image or video processing system of interest. KEYWORDSReal-time image and video processing, Real-time implementation strategies, Algorithmic simplifications for real-time image and video processing, Hardware platforms for real-time image and video processing, Software methods for real-time image and video processing v

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Real-time 2-D wavelet transform implementation for HDTV compression

Cited by 15 publications

References 16 publications

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Design and implementation of optimized architecture for computing the 2D‐DWT for JPEG2000 compression

Real-Time Image and Video Processing: From Research to Reality

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