Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding

Dawid, H.; Meyr, H.

doi:10.1109/pimrc.1995.476882

Cited by 36 publications

(28 citation statements)

References 11 publications

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“…Figure 11 shows implementation of SW SISO MAP decoder (Dawid & Meyr, 1995), and a comparison of hardware requirement is made between the implementation of SW SISO MAP decoder with the standard SISO MAP decoder. Figure 11 shows that for SW SISO MAP decoder, hardware requirement is higher than in case of standard SISO MAP decoder as SW SISO MAP decoder uses time multiplexing to reduce the latency.…”

Section: Sliding Window Siso Map Decodermentioning

confidence: 99%

High-performance VLSI architectures for turbo decoders with QPP interleaver

Verma

Kumar

2014

International Journal of Electronics

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This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW -SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

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Section: Sliding Window Siso Map Decodermentioning

confidence: 99%

High-performance VLSI architectures for turbo decoders with QPP interleaver

Verma

Kumar

2014

International Journal of Electronics

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“…To reduce both the memory requirements and the latency, a sliding window algorithm (SW) is used [7]. Using the same graphical representation as in [3], our modified SW-FB algorithm with windows of size L symbols is depicted in Fig.…”

Section: Algorithm Architecture Matchingmentioning

confidence: 99%

Constrained algorithmic IP design for system-on-chip

Coussy¹,

Casseau²,

Bomel³

et al. 2007

Integration

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“…Latency and memory size are significantly reduced by the sliding window approach [3], [20]- [22]. Backward (and/or forward) metrics are initialized at an intermediate point instead of the end or the beginning of the block.…”

Section: B Decodermentioning

confidence: 99%

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Dobkin

Peleg

Ginosar

2005

IEEE Trans. VLSI Syst.

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Abstract-Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.Index Terms-Decoders, interleaver, maximum a posteriori (MAP) algorithm, parallel architecture, turbo codes, VLSI architecture.

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Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding

Cited by 36 publications

References 11 publications

High-performance VLSI architectures for turbo decoders with QPP interleaver

High-performance VLSI architectures for turbo decoders with QPP interleaver

Constrained algorithmic IP design for system-on-chip

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

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