Real time astrocyte in spiking neural network

IET Computers & Digital Techniques

et al. 2018

Hardware has become more prone to faults as a result of geometric scaling, wear-out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self-repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self-repair within models of neural networks known as neuro-glia networks. This astrocyte-driven repair process can address the issues of faulty synapse connections between neurons. These astrocyte cells are distributed throughout a neuro-glia network and regulate synaptic activity, and it has been observed in computational models that this can result in a fine-grained self-repair process. Therefore, mapping neuro-glia networks to hardware provides a strategy for achieving self-repair in hardware. The internal interconnecting of these networks in hardware is a challenge. Previous work has focused on addressing neuron to astrocyte communication (local), however, the global self-repair process is dependent on the communication infrastructure between astrocyte-to-astrocyte; e.g. astrocyte network. This paper addresses the key challenge of providing a scalable communication interconnect for global astrocyte network requirements and how it integrates with existing local communication mechanism. Area/power results demonstrate scalable implementations with the ring topology while meeting timing requirements.

Section: Introductionmentioning

confidence: 75%

Section: Hierarchical Network-on-chipmentioning

confidence: 99%

On‐chip communication for neuro‐glia networks

Martin

IET Computers & Digital Techniques

et al. 2018

“…Each neuron is connected to an astrocyte in this model and improvements have been reported over traditional Artificial Neural Networks (ANN)s and other NGNs in terms of solving classification problems [9]. Astrocytes have also been used to increase firing rates at tripartite synapses [10]. Here the internal calcium pool of the astrocyte is excited by two mechanisms.…”

Section: A Software Implementationsmentioning

confidence: 99%

Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks

Karim

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

et al. 2017

This paper presents a hardware based implementation of a biologically-faithful astrocyte-based selfrepairing mechanism for Spiking Neural Networks. Spiking Astrocyte-neuron Networks (SANNs) are a new computing paradigm which capture the key mechanisms of how the human brain performs repairs. Using SANN in hardware affords the potential for realizing computing architecture that can self-repair. This paper demonstrates that Spiking Astrocyte Neural Network (SANN) in hardware have a resilience to significant levels of faults. The key novelty of the paper resides in implementing an SANN on FPGAs using fixed-point representation and demonstrating graceful performance degradation to different levels of injected faults via its self-repair capability. A fixed-point implementation of astrocyte, neurons and tripartite synapses are presented and compared against previous hardware floating-point and Matlab software implementations of SANN. All results are obtained from the SANN FPGA implementation and show how the reduced fixedpoint representation can maintain the biologically-realistic repair capability.

“…Recent work has implemented astrocyte cells in neuromorphic systems [8], [9] and digital circuits [10]- [13] with the aim of exploring their behaviour. None have considered the challenge of facilitating scalable interconnect for neuro-glia networks.…”

Section: From Biology To Hardwarementioning

confidence: 99%

Astrocyte to spiking neuron communication using Networks-on-Chip ring topology

Martin

2016 IEEE Symposium Series on Computational Intelligence (SSCI)

et al. 2016

Hardware faults are becoming more frequent due to geometric scaling, reducing the reliability and lifespan of devices. Current fault-tolerant approaches use redundancy or a central controller to detect and/or repair faults. However, these methods are also susceptible to faults. Astrocytes have been shown to facilitate biological self-repair in silent or near silent neurons in the brain by increasing the Probability of Release (PR) in healthy synapses. Astrocytes modulate synaptic activity, which leads to increased or decreased PR. To date, this has been proven with computational modelling and therefore the next step is to replicate this self-repair process in hardware to provide self-repairing systems. One of the key challenges for hardware neuro-glia networks is the facilitation of scalable communication between interacting neurons and astrocyte cells. This paper contributes a low-level Networks-on-Chip (NoC) ring topology for astrocyte to neuron/synapse communication which provide a scalable solution to this interconnect challenge. This work extends our current FPGA-based Hierarchical Networks-on-Chip (HNoC). FPGA results demonstrates that the new ring topology provides a good trade-off between low area/interconnect wiring overhead and communication speed for the relatively slow-changing data between astrocyte and neurons.