Recent Progress on Signal Integrity Modeling of Neuromorphic Chips by the PEEC Method

Ma, Hanzhi; Tao, Tuomin; Chen, Quankun; Li, Da; Schutt-Aine, Jose; Cangellaris, Andreas; Li, Er-Ping

doi:10.1109/epeps58208.2023.10314875

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2023

2024

Publication Types

Select...

Other2

Article1

Relationship

Self Cite1

Independent2

Authors

Journals

Cited by 3 publications

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Latency Insertion Method for Accelerated Simulation of Memristor Crossbar Array in Neuromorphic Chip

Zhou,

Ma,

et al. 2024

2024 IEEE 74th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Latency Insertion Method for Accelerated Simulation of Memristor Crossbar Array in Neuromorphic Chip

Zhou,

Ma,

et al. 2024

2024 IEEE 74th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

A One-Hot Encoding Approach for Signal Integrity Enhancement of Intra-chip Interconnects

Sun,

Wu,

Guo

et al. 2024

2024 25th International Conference on Electronic Packaging Technology (ICEPT)

View full text Add to dashboard Cite

An Electromagnetic Perspective of Artificial Intelligence Neuromorphic Chips

Li,

Ma,

Ahmed

et al. 2023

Electromag. Sci.

Self Cite

View full text Add to dashboard Cite

The emergence of artificial intelligence has represented great potential in solving a wide range of complex problems. However, traditional general-purpose chips based on von Neumann architectures face the "memory wall" problem when applied in artificial intelligence applications. Based on the efficiency of the human brain, many intelligent neuromorphic chips have been proposed to emulate its working mechanism and neuron-synapse structure. With the emergence of spiking-based neuromorphic chips, the computation and energy efficiency of such devices could be enhanced by integrating a variety of features inspired by the biological brain. Aligning with the rapid development of neuromorphic chips, it is of great importance to quickly initiate the investigation of the electromagnetic interference and signal integrity issues related to neuromorphic chips for both CMOS-based and memristor-based artificial intelligence integrated circuits. Here, this paper provides a review of neuromorphic circuit design and algorithms in terms of electromagnetic issues and opportunities with a focus on signal integrity issues, modeling, and optimization. Moreover, the heterogeneous structures of neuromorphic circuits and other circuits, such as memory arrays and sensors using different integration technologies, are also reviewed, and locations where signal integrity might be compromised are discussed. Finally, we provide future trends in electromagnetic interference and signal integrity and outline prospects for upcoming neuromorphic devices.

show abstract

Recent Progress on Signal Integrity Modeling of Neuromorphic Chips by the PEEC Method

Cited by 3 publications

References 15 publications

Latency Insertion Method for Accelerated Simulation of Memristor Crossbar Array in Neuromorphic Chip

Latency Insertion Method for Accelerated Simulation of Memristor Crossbar Array in Neuromorphic Chip

A One-Hot Encoding Approach for Signal Integrity Enhancement of Intra-chip Interconnects

An Electromagnetic Perspective of Artificial Intelligence Neuromorphic Chips

Contact Info

Product

Resources

About