Reconfigurable intra prediction hardware for future video coding

An Efficient FPGA Implementation of Versatile Video Coding Intra Prediction

“…In VVC, each intra angular prediction equation requires four multiplication operations to multiply four pixels with corresponding filter coefficients and three addition operations to add the results of these four multiplications. Therefore, four DSP blocks are necessary for implementing an intra angular prediction equation in its original form as in [11]. In the proposed FPGA implementation, intra angular prediction equations are manipulated in such a way that one intra angular prediction equation is implemented using two DSP blocks and two adders.…”

“…The proposed VVC intra prediction hardware is compared with HEVC and VVC intra prediction hardware in the literature in Table III. Since VVC intra prediction algorithm is more complex than HEVC intra prediction algorithm, the proposed VVC intra prediction hardware implementation and the two VVC intra prediction hardware implementations proposed in [11] are slower and have more area than the HEVC intra prediction hardware implementations [12]- [15].…”

“…RECON_AS hardware implements VVC intra prediction using adders and shifters [11]. It does not use DSP blocks.…”

“…It does not use DSP blocks. RECON_DSP hardware implements VVC intra prediction using DSP blocks [11]. It uses four DSP blocks and one adder for implementing an intra angular prediction equation.…”

“…Two VVC intra prediction hardware implementations are proposed in [11]. Several HEVC intra prediction hardware implementations are proposed in the literature [12]- [15].…”