Reconfigurable optical interconnects for parallel computer systems: design space issues

Abstract

In highly parallel computer systems, reconfigurable interconnect network topologies can improve the performance by adaptively increasing the communication bandwidth where it is most needed. In electrical reconfigurable interconnect networks (e.g. crossbars or multi-stage networks), a high reconfigurability can only be achieved at the cost of both chip area and network latency. The facts that short-distance optical link latencies are rapidly decreasing and that new technologies allow optical reconfigurability, make optical interconnects an interesting alternative to overcome these interconnection issues. Optical interconnection technologies indeed offer several possibilities to increase network connectivity without drastically increasing the chip area and the delay costs. In this paper we study the bandwidth and latency requirements of inter-processor and processor-memory interconnect for shared-memory parallel computers when the processor clock increases up to 10 GHz. We also investigate new enabling technologies and discuss their potential use in architectures based on reconfigurable optical interconnects.