Reduce SW/HW Migration Efforts by a RTOS in Multi-FPGA Systems

Zhou, Bo; Chen, Yonghui; Qiu, Weidong; Chen, Yan; Peng, Chenglian

doi:10.1007/11686699_64

Cited by 1 publication

(2 citation statements)

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“…Accordingly, the utilization of hardware threads is seriously degraded. Another example is the SHUM-μC/OS project proposed by Zhou et al [11]. Zhou et al modified the μC/OS-II RTOS and defined their hardware thread model.…”

Section: Related Workmentioning

confidence: 99%

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Function-Level Multitasking Interface Design in an Embedded Operating System with Reconfigurable Hardware

Huang

Wang

Chu

et al.

Embedded and Ubiquitous Computing

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Abstract. Reconfigurable architecture provides a high performance computing paradigm. We can implement the compute-intensive functions into reconfigurable devices to optimize the application performance. In current reconfigurable hardware designs, the function-level reconfigurable hardware has high reusability and low maintenance cost. However, the sharing mechanism and the function invocation interface are still unknown. In this paper, we propose a function-level multitasking interface design to support reconfigurable component sharing in a multitasking embedded operating system. The reconfigurable hardware functions are managed and scheduled by the operating system. Applications can use any needed hardware function via invocation APIs. To study the performance impacts, we implemented a prototype on Altera SOPC development board. We modified μC/OS-II RTOS and evaluated the prototype with prime number search programs and loop programs. The experimental results show the management overhead is acceptable.

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Section: Related Workmentioning

confidence: 99%

“…The acceleration granularity employed in the second category focuses on the task level [2,11]. In this task-level acceleration approach, tasks can be either software-coded or implemented as hardware units.…”

Section: Introductionmentioning

confidence: 99%