Reduced-memory high-throughput fast-SSC polar code decoder architecture

Ercan, Furkan; Condo, Carlo; Gross, Warren J.

doi:10.1109/sips.2017.8110014

Cited by 30 publications

(49 citation statements)

References 11 publications

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“…And the throughput of the proposed decoder is 1.3 times greater than that. It shows that either the latency or the throughput of this work is better than that in [20,24,25]. O. Dizdar and E. Arikan proposed a deeply pipelined polar decoder based on SC decoding algorithm.…”

Section: 3mentioning

confidence: 87%

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High‐Throughput Fast‐SSC Polar Decoder for Wireless Communications

Zhang

Yan

Zeng

et al. 2018

Wireless Communications and Mobile Computing

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Polar code has been proven to achieve the symmetric capacity of memoryless channels. However, the successive cancellation decoding algorithm is inherent serial in nature, which will lead to high latency and low throughput. In order to obtain high throughput, we design a deeply pipelined polar decoder and optimize the processing elements and storage structure. We also propose an improved fixed-point nonuniform quantization scheme, and it is close to the floating-point performance. Two-level control strategy is presented to simplify the controller. In addition, we adopt FIFO structure to implement the memory and memory and propose the 348-stage pipeline decoder.

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Section: 3mentioning

confidence: 87%

“…However, it costs less registers compared with [20]. For the decoder in [24], it costs less resource because it does not adopt deeply pipelined architecture.…”

Section: Resource Consumptionmentioning

confidence: 99%

High‐Throughput Fast‐SSC Polar Decoder for Wireless Communications

Zhang

Yan

Zeng

et al. 2018

Wireless Communications and Mobile Computing

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“…In the spirit of further reducing the latency, Yuan et al [98] proposed a 2-bit decoding architecture for SC decoders, which concurrently processes two bits during the last stage of the SC decoding process. Look-ahead techniques were also invoked in [98] and recently in [129], while memory-efficient hardware implementations were presented in [124], [130].…”

Section: A Successive Cancellation (Sc) Decodermentioning

confidence: 99%

Polar Codes and Their Quantum-Domain Counterparts

Babar

Egilmez

Xiang

et al. 2020

IEEE Commun. Surv. Tutorials

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Arikan's polar codes are capable of achieving the Shannon's capacity at a low encoding and decoding complexity, while inherently supporting rate adaptation. By virtue of these attractive features, polar codes have provided fierce competition to both the turbo as well as the Low Density Parity Check (LDPC) codes, making its way into the 5G New Radio (NR). Realizing the significance of polar codes, in this paper we provide a comprehensive survey of polar codes, highlighting the major milestones achieved in the last decade. Furthermore, we also provide tutorial insights into the polar encoder, decoders as well as the code construction methods. We also extend our discussions to quantum polar codes with an emphasis on the underlying quantum-to-classical isomorphism and the syndromebased quantum polar codes.

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“…Compared to conventional SC decoder implementations [5], Fast-SSC decoding is shown to F. Ercan improve the throughput by an order of magnitude. Further identification and use of special nodes were carried out in both SC-based [1], [6], [7] and SC-List based [9], [10] decoding techniques.…”

Section: Introductionmentioning

confidence: 99%

Operation Merging for Hardware Implementations of Fast Polar Decoders

Ercan

Tonnellier

Condo

et al. 2018

J Sign Process Syst

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Polar codes are a class of linear block codes that provably achieves channel capacity. They have been selected as a coding scheme for the control channel of enhanced mobile broadband (eMBB) scenario for 5 th generation wireless communication networks (5G) and are being considered for additional use scenarios. As a result, fast decoding techniques for polar codes are essential. Previous works targeting improved throughput for successive-cancellation (SC) decoding of polar codes are semiparallel implementations that exploit special maximum-likelihood (ML) nodes. In this work, we present a new fast simplified SC (Fast-SSC) decoder architecture. Compared to a baseline Fast-SSC decoder, our solution is able to reduce the memory requirements. We achieve this through a more efficient memory utilization, which also enables to execute multiple operations in a single clock cycle. Finally, we propose new special node merging techniques that improve the throughput further, and detail a new Fast-SSC-based decoder architecture to support merged operations. The proposed decoder reduces the operation sequence requirement by up to 39%, which enables to reduce the number of time steps to decode a codeword by 35%. ASIC implementation results with 65 nm TSMC technology show that the proposed decoder has a throughput improvement of up to 31% compared to previous Fast-SSC decoder architectures.

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Reduced-memory high-throughput fast-SSC polar code decoder architecture

Cited by 30 publications

References 11 publications

High‐Throughput Fast‐SSC Polar Decoder for Wireless Communications

High‐Throughput Fast‐SSC Polar Decoder for Wireless Communications

Polar Codes and Their Quantum-Domain Counterparts

Operation Merging for Hardware Implementations of Fast Polar Decoders

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