Reducibility of sequential test generation to combinational test generation for several delay fault models

Abstract

This paper presents a new structure, called discontinuous reconvergence structure (DR-structure), of sequential circuits with easy testability for delay faults. We show that the delay fault test generation problem for sequential circuits with DR-structure can be reduced to that for their time-expansion models, which are combinational circuits. Based on the reducibility, we propose a test generation method for delay faults in sequential circuits with DRstructure. This method can be applied to several delay fault models. By some experiments, we show that the proposed method is effective in the hardware overhead, the test generation time and the fault efficiency.