Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

Abstract

Systems-on-Chip (SoCs) with a large number of cores adopt Networks-on-chip (NoCs) as the communication infrastructure due to its scalability. The complexity to distribute a skew-free synchronous clock signal over the entire chip increases in current fabrication technologies due to the process variability. Thus, designers may choose among fully asynchronous and Globally Asynchronous, Locally Synchronous (GALS) NoCs. This work proposes an intermediate solution. Each Intellectual Property (IP) core may have its clock domain, and the NoC supports both synchronous and asynchronous communication. The NoC has its own clock domain, with the synchronous communication used to establish end-to-end paths. Once the end-to-end path is established, the NoC connects the IPs asynchronously, as wires with repeaters. The message is transmitted using handshake protocol at the source IP frequency. The benefit of the proposal is the reduction in the communication energy consumption (up to 52%). The cost is a latency increase (16% to 30%) and area overhead (4%).

Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC

“…Several efforts are being dedicated toward optimizing NoC designs for overall power reduction [5,6,9]. Recently, asynchronous techniques for NoCs gained popularity, and different designs were introduced.…”

“…For synchronous systems, clock gating was introduced to lessen the dynamic power consumption [8]. The globally asynchronous locally synchronous (GALS) design paradigm was established specifically for system-on-chip (SoC) [9]. It addresses the clock skew obstacle, reduces the overall power consumption and maintains high system performance.…”

“…It addresses the clock skew obstacle, reduces the overall power consumption and maintains high system performance. GALS systems are considered the incentive for the rise of asynchronous designs specifically for communication purposes [9,10].…”