Reducing radiation-hardened DigitalCircuit power consumption

McIver, John K.; Clark, Lawrence T.

doi:10.1109/tns.2005.861082

Cited by 3 publications

(2 citation statements)

References 20 publications

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“…The major element of the shift register type circuit blocks is made by the D-flip flop (FF) circuit. 25,26) D-FF is made by a master-slave type, which consists of two D-latch connected to each other. D data is acquired at the rising edge of the clock, then output data to Q at the falling edge.…”

Section: Two-dimensional Array Data Transfer Logic Circuitsmentioning

confidence: 99%

Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18 μm CMOS technology

Yoda

Ishihara

Oshima

et al. 2022

Jpn. J. Appl. Phys.

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Circuits for CMOS two-dimensional (2-D) array data transfer are indispensable for applications such as space and nuclear fields. Issues include to be operated with higher speed, lower power, fewer size penalty and radiation hardness. To meet these requirements, two kinds of CMOS 2-D array data transfer circuits, such as a shift register type and a memory access type, are proposed and fabricated by the standard 0.18-µm CMOS process technology. In the both types, 16 µm pitch, 8×124 array data transfer operations were realized with data rate of more than 1 Gb/s. Furthermore, we conducted 60Co γ-ray irradiation experiments on those circuits. The current consumption ratio of the shift register type to the memory access type ranges from 150 to 200% as the dosage increases. The result indicate that the memory access type has better radiation hardness at 1 Gb/s than that of the shift register type.

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Section: Two-dimensional Array Data Transfer Logic Circuitsmentioning

confidence: 99%

Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18 μm CMOS technology

Yoda

Ishihara

Oshima

et al. 2022

Jpn. J. Appl. Phys.

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“…A differential cascode voltage switch logic based radiation‐hardened system [18] functioned with an integral level shift and allows storage at the full supply voltage supported by the process. It is supported for sequential digital circuits because of aware of multiple supply voltages, integrated logic, and a low standby power state.…”

Section: Introductionmentioning

confidence: 99%

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

Kamalakannan¹,

Venkatachalam²

2019

IET Circuits, Devices & Systems

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The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip-flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

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