Relative logic cell placement for mitigation of charge sharing-induced transients

Abstract

Design of modern integrated circuits increasingly requires consideration of radiation effects, especially in space and other high-risk environments. With fabrication technologies scaling down both feature sizes and critical charge, a radiation strike in sub-100 nm technologies may affect multiple, physically adjacent nodes. With increasing clock speeds, transient errors in the processing datapath also increase in risk. Modeling single-event multiple-transients (SEMT) for pre-fabrication reliability characterization has become a more common design step, and this work adds to the state-of-the-art by providing a fast and physically-informed characterization flow that captures the effects of single-event multiple-node charge collection through experimentally observed transport mechanisms. Beyond characterization, the study of SEMT vulnerabilities reveals the electronic design automation (EDA) step of standard logic cell placement as a design space for hardening against SEMT-induced errors. This work: (1) analyzes the vulnerability of benchmark circuits against SEMT errors, (2) evaluates the impact of logic on transient propagation, (3) explores EDA placement techniques, and (4) builds an automated design flow for relative placement of cells to mask transient errors, while maintaining compatibility with other radiation hardening techniques. Zero cost to area and marginal impact on timing enable this new cell placement algorithm that masks 30% of SEMT-induced errors.