Reliable Extractions of EOT and Vfb in Poly-Si Gate High-k MISFETs through Advanced Modeling of Gate and Substrate Capacitances

Two-step annealing effects on ultrathin EOT higher-k (k &#x003D; 40) ALD-HfO<inf>2</inf> gate stacks

“…The ideal C-V curve for 0.25 nm EOT is also plotted in the figure, which is simulated by considering the quantization capacitance at the high-k/Si interface. [13] The ideal C-V curve shows good agreement with that for the 2.4-nm-thick HfO 2 gate stack. This implies that the very large accumulation capacitance corresponds to the very small EOT (0.25 nm).…”

Hafnium silicate gate dielectrics in GaN metal oxide semiconductor capacitors

“…The flatband voltage (V fb ) and capacitance equivalent thickness (CET) values for each specimen were estimated from the C-V data using a MIRAI-ACCEPT software. 32,33) The Hf:Si ratios in the HfO 2 /SiO 2 laminates made with ALD cycle ratios of 2/1 and 3/1 were estimated to be 0.57:0.43 (Hf 0.57 Si 0.43 O x ) and 0.64:0.36 (Hf 0.64 Si 0.36 O x ), respectively, based on EDS data. A cross-sectional TEM image of the Pt/Hf 0.64 Si 0.36 O x /n-GaN MOS capacitor after PDA at 800 °C is shown in Fig.…”

Improvement of Device Characteristics for TiN Gate p-Type Metal–Insulator–Semiconductor Field-Effect Transistor with Al2O3-Capped HfO2 Dielectrics by Controlling Al2O3 Diffusion Annealing Process

“…The EOT was analytically calculated using a program that takes into account quantum mechanics, called MIRAI-ACCEPT [the analytical capacitance calculator for extraction of precise thickness proposed by the Millennium Research for Advanced Information Technology (MIRAI) project]. 11) The V t variation of pMISFETs was analyzed with the standard deviation of the random offset of 21 sets of paired pMISFETs, ÁV t . Each of the 21 sets of paired pMISFETs were located throughout the wafer of 300 mm diameter.…”