Reliable router architecture with elastic buffer for NoC architecture

Abstract

Router is the basic building block of the interconnection network. In this paper, new router architecture with elastic buffer is proposed which is reliable and also has less area and power consumption. The proposed router architecture is based on new error detection mechanisms appropriate for dynamic NoC architectures. It considers data packet error detection, correction and also routing errors. The uniqueness of the reliable router architecture is to focus on finding error sources accurately. This technique differentiates permanent and transient errors and also protects diagonal availabilities. Input and output buffers in router architectures are replaced by elastic buffers. Routers spend considerable area and power for router buffer. In this paper the proposed router architecture replaces FIFO buffers with the elastic buffers in order to reduce area, and power consumption and also to have better performance.

Low power network on chip architectures: A survey

“…Gladiator et al [13] planned router design for the replaces of FIFO buffers with expansible buffers in tells to the trammel extent, then nation uptake and to the individual meliorates show. Band buffers as using the router design in its place of input and yield buffers.…”

Low power network on chip architectures: A survey

“…Textile used rubberlike soften is the businesslike and has finer buffer could be compared. Certain router design with adaptable cowcatcher takes inferior zone and force intake and takes outperform action [13].…”

“…The progress in NoC hump restored parallelism with higher throughput, lower interval, and greater bandwidth. Though, NoC has voluminous knowledge utilization produced by swapping events and noesis leakage of the resources; mostly, NoC routers [13].…”