Repeater insertion in power-managed VLSI systems

Abstract

In this paper, design space exploration methods for interconnect repeaters in DSM power-managed VLSI are proposed. These methods guarantee that the designed interconnects are energyoptimal, while they meet their performance objectives in all the system operating states. These methods take the dynamic output resistance characteristic of the repeaters into account, when the system operating voltage and/or operating frequency requirement changes. Utilizing the proposed design methods, a multi-cycle bus is designed for some performance targets. HSPICE simulations confirm that the designed bus is energy-optimal, and it meets its performance objectives in all the system operating states.