Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Abstract

With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs.