Resilient Low Voltage Accelerators for High Energy Efficiency

Chandramoorthy, Nandhini; Swaminathan, Karthik; Cochet, Martin; Paidimarri, Arun; Eldridge, Schuyler; Joshi, Rajiv V.; Ziegler, Matthew M.; Buyuktosunoglu, Alper; Bose, Pradip

doi:10.1109/hpca.2019.00034

Cited by 35 publications

(48 citation statements)

References 32 publications

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“…However, these guardbands can be very conservative and unnecessary for state-of-the-art applications. Supply voltage underscaling below the nominal level was already shown to provide significant efficiency improvements in CPUs [78], GPUs [138,66], ASICs [17], and DRAMs [18,50]. This paper extends such studies to FPGAs.…”

Section: Introductionmentioning

confidence: 61%

“…Undervolting of real hardware is studied for various system components, such as CPUs [8,76,77,43,10], GPUs [138,55,56], ASICs [17,75,48], DRAMs [18,19,50], and Flash disks [14,15,16]. These studies focus on voltage guardband analysis, fault characterization, and fault mitigation.…”

Section: Undervoltingmentioning

confidence: 99%

“…Our work uses an industrial tool [122] that inherently exploits these techniques. • Undervolting: Undervolting has been shown to provide significant power-efficiency benefit for CNNs when applied to SRAMs [17], DRAMs [50], ASICs [68,132,128,17,48], and heterogeneous systems [24,25,100].…”

Section: Power-efficient Cnnsmentioning

confidence: 99%

“…In real-world applications, such as IoT, airspace, and driver-less cars, CNNs can potentially experience different types of faults. Various works evaluate CNN reliability on faulty real hardware, e.g., soft errors [61,62,112,13] and undervolting in ASICs [59,17,116,117,54]. This approach requires significant engineering effort but can result in relatively more accurate results.…”

Section: Reliability Of Cnnsmentioning

confidence: 99%

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An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

Salami¹,

Onural

Yüksel

et al. 2020

2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators.We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W ) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.

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Section: Introductionmentioning

confidence: 61%

Section: Undervoltingmentioning

confidence: 99%

Section: Power-efficient Cnnsmentioning

confidence: 99%

Section: Reliability Of Cnnsmentioning

confidence: 99%

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An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

Salami¹,

Onural

Yüksel

et al. 2020

2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

View full text Add to dashboard Cite

show abstract

“…Hence, recently, the resilience of DNNs has been studied in different abstraction levels. A vast majority of the previous works in this area belong to the DNN inference phase, including simulationbased efforts [33]- [36] and works on the real hardware [12], [37]- [39]. The verification of the simulation-based works on the real fabric can be a crucial concern; also, the real hardware works are mostly performed on the customized ASICs, which of course, reproducing those results on the COTS systems is a crucial question.…”

Section: Related Workmentioning

confidence: 99%

On the Resilience of Deep Learning for Reduced-voltage FPGAs

Givaki

Salami

Hojabr

et al. 2020

2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

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Deep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solution that can satisfy these requirements for both embedded and High-Performance Computing (HPC) systems. In FPGAs, as well as CPUs and GPUs, aggressive voltage scaling below the nominal level is an effective technique for power dissipation minimization. Unfortunately, bit-flip faults start to appear as the voltage is scaled down closer to the transistor threshold due to timing issues, thus creating a resilience issue. This paper experimentally evaluates the resilience of the training phase of DNNs in the presence of voltage underscaling related faults of FPGAs, especially in on-chip memories. Toward this goal, we have experimentally evaluated the resilience of LeNet-5 and also a specially designed network for CIFAR-10 dataset with different activation functions of Rectified Linear Unit (Relu) and Hyperbolic Tangent (Tanh). We have found that modern FPGAs are robust enough in extremely low-voltage levels and that low-voltage related faults can be automatically masked within the training iterations, so there is no need for costly software-or hardware-oriented fault mitigation techniques like ECC. Approximately 10% more training iterations are needed to fill the gap in the accuracy. This observation is the result of the relatively low rate of undervolting faults, i.e., <0.1%, measured on real FPGA fabrics. We have also increased the fault rate significantly for the LeNet-5 network by randomly generated fault injection campaigns and observed that the training accuracy starts to degrade. When the fault rate increases, the network with Tanh activation function outperforms the one with Relu in terms of accuracy, e.g., when the fault rate is 30% the accuracy difference is 4.92%.

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