Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing

Guo, Qing; Guo, Xiaochen; Bai, Yuxin; Patel, Ravi B.; Ïpek, Engin; Friedman, Eby G.

doi:10.1109/mm.2015.89

Cited by 22 publications

(5 citation statements)

References 6 publications

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“…Before the search operation, the input data is stored in the buffer, and the buffer strengthens the input signals to ensure every row can receive the input signals at the same time. A typical way to differentiate the HDs of stored values to the input signal is to exploit a timing characteristic of the discharging current for each row [38], [39]. In this approach, for the search operation, match lines (ML) of all rows are precharged to V dd.…”

Section: B Rna Am-based Computationmentioning

confidence: 99%

RAPIDNN: In-Memory Deep Neural Network Acceleration Framework

Imani,

Samragh,

Kim

et al. 2018

Preprint

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Deep neural networks (DNN) have demonstrated effectiveness for various applications such as image processing, video segmentation, and speech recognition. Running state-ofthe-art DNNs on current systems mostly relies on either generalpurpose processors, ASIC designs, or FPGA accelerators, all of which suffer from data movements due to the limited on-chip memory and data transfer bandwidth. In this work, we propose a novel framework, called RAPIDNN, which performs neuron-tomemory transformation in order to accelerate DNNs in a highly parallel architecture. RAPIDNN reinterprets a DNN model and maps it into a specialized accelerator, which is designed using non-volatile memory blocks that model four fundamental DNN operations, i.e., multiplication, addition, activation functions, and pooling. The framework extracts representative operands of a DNN model, e.g., weights and input values, using clustering methods to optimize the model for in-memory processing. Then, it maps the extracted operands and their pre-computed results into the accelerator memory blocks. At runtime, the accelerator identifies computation results based on efficient inmemory search capability which also provides tunability of approximation to improve computation efficiency further. Our evaluation shows that RAPIDNN achieves 68.4×, 49.5× energy efficiency improvement and 48.1×, 10.9× speedup as compared to ISAAC and PipeLayer, the state-of-the-art DNN accelerators, while ensuring less than 0.5% quality loss.

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Section: B Rna Am-based Computationmentioning

confidence: 99%

RAPIDNN: In-Memory Deep Neural Network Acceleration Framework

Imani,

Samragh,

Kim

et al. 2018

Preprint

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“…Unlike DRAMs, bit-line computing may work well in a diverse set of nonvolatile memory technologies (RRAMs, STT-MRAMs, and Flash). Researchers have already found success in repurposing structures in emerging NVMs to build efficient ternary content-addressable memory (TCAM) 26 and neural networks. [27][28][29] Computational memories can be massively data parallel-potentially, an order of magnitude more performance and energy efficient than modern data-parallel accelerators such as GPUs.…”

Section: Ieee Micromentioning

confidence: 99%

Blurring the Lines between Memory and Computation

Das

2017

IEEE Micro

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“…[23,24] Recently, in order to further improve the data storage density, researchers have designed and developed RRAM with multilevel storage performance. [25][26][27][28][29][30][31][32][33] This kind of multi-level memory has the potential to achieve a storage capacity of 3 n or even greater, and can better meet the needs of future computing systems than ordinary binary memories. Among them, the donor-acceptor (D-A) polymer has attracted wide attention because of its structural adjustability and the realization of multilevel storage through charge transfer between the donor and acceptor.…”

Section: Introductionmentioning

confidence: 99%

Ternary Memory Behavior of Carbazole‐Based Donor–Acceptor Polymer and CdS NPs Composites

Dou

Zhao

Gao

et al. 2022

Macro Chemistry & Physics

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Multi-level memory can greatly improve information density, so it has been widely studied. In this study, a carbazole-based donor-acceptor polymer poly[2,7-9-(heptadecan-9-yl)-9H-carbazole-alt-7H-benzimidazo[2,1a]benz[de]isoquinolin-7-one] (PCz-BB) is synthesized, which exhibits flash-type ternary memory behavior. Further, CdS nanoparticles (NPs) are embedded into the prepared polymer to enhance the storage performance. The current-voltage (I-V) characteristics of memory devices based on PCz-BB:CdS composites and the effect of the embedding ratio of CdS NPs on the memory devices are studied. It is verified that the ON2/ON1/OFF current ratios of the devices at low CdS embedding concentrations are improved, and the threshold voltages are also reduced. The memory device based on the optimal embedding concentration (3 wt% CdS) exhibits a high ON2/ON1/OFF current ratio of 18631:72:1, a low threshold voltage of −0.40/−1.20 V, and excellent stability. The mechanism of resistive switching is explained by the theory of charge traps and conductive filaments. This work provides a new avenue for high-performance multi-level organic electrical storage materials.

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Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing

Cited by 22 publications

References 6 publications

RAPIDNN: In-Memory Deep Neural Network Acceleration Framework

RAPIDNN: In-Memory Deep Neural Network Acceleration Framework

Blurring the Lines between Memory and Computation

Ternary Memory Behavior of Carbazole‐Based Donor–Acceptor Polymer and CdS NPs Composites

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